[wwwdocs] projects/prefetch.html -- replace direct formatting of tables with CSS

[Gerald Pfeifer]

On Sun, 2 Sep 2018, Gerald Pfeifer wrote:
> Committed.

Buiding on my changes last Sunday, this uses the new class "border"
I introduced earlier today, thus avoiding validation warnings.

Committed.

Gerald

Index: projects/prefetch.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/projects/prefetch.html,v
retrieving revision 1.37
diff -u -r1.37 prefetch.html
--- projects/prefetch.html	2 Sep 2018 15:11:38 -0000	1.37
+++ projects/prefetch.html	9 Sep 2018 20:20:40 -0000
@@ -208,7 +208,7 @@
 
 <h3 id="summary">Summary</h3>
 
-<table class="padding5" border="1">
+<table class="border padding5">
 <tr>
   <th>Target</th>
   <th>Prefetch amount</th>
@@ -333,7 +333,7 @@
 Instruction <code>LDS</code> with a destination of register <code>F31</code>
 prefetches for a store.</p>
 
-<table class="padding5" border="1">
+<table class="border padding5">
 <tr>
   <td><code>LDBU</code>, <code>LDF</code>, <code>LDG</code>, <code>LDL</code>,
       <code>LDT</code>, <code>LDWU</code></td>
@@ -358,7 +358,7 @@
 <p>The Alpha architecture also defines the following instructions
 [<a href="#ref_2">2</a>]:</p>
 
-<table class="padding5" border="1">
+<table class="border padding5">
 <tr>
   <td><code>FETCH</code></td>
   <td>Prefetch Data</td>
@@ -380,7 +380,7 @@
 <em>data stream</em> made up of the following elements
 [<a href="#ref_4">4</a>].:</p>
 
-<table class="padding5" border="1">
+<table class="border padding5">
 <tr>
   <td>EA</td>
   <td>the effective address of the first unit in the sequence;
@@ -405,7 +405,7 @@
 
 <p>The instructions that operate on these data streams are:</p>
 
-<table class="padding5" border="1">
+<table class="border padding5">
 <tr>
   <td><code>dst</code></td>
   <td>(Data Stream Touch); data marked as most recently used
@@ -474,7 +474,7 @@
 
 <p>The SSE <code>prefetch</code> instruction has the following variants:</p>
 
-<table class="padding5" border="1">
+<table class="border padding5">
 <tr>
   <td><code>prefetcht0</code></td>
   <td>Temporal data; prefetch data into all cache levels.</td>
@@ -508,7 +508,7 @@
 
 <p>The possible values for the locality hint are:</p>
 
-<table class="padding5" border="1">
+<table class="border padding5">
 <tr>
   <td>none</td>
   <td>Temporal locality for cache level 1 and higher (all levels).</td>
@@ -545,7 +545,7 @@
 [<a href="#ref_9">9</a>] and MIPS64 [<a href="#ref_10">10</a>],
 takes a hint with one of the following values:</p>
 
-<table class="padding5" border="1">
+<table class="border padding5">
 <tr>
   <td><code>load</code></td>
   <td>data is expected to be read, not modified</td>
@@ -598,7 +598,7 @@
 <p>MMIX has the following data prefetch instructions
 [<a href="#ref_11">11</a>][<a href="#ref_12">12</a>]:</p>
 
-<table class="padding5" border="1">
+<table class="border padding5">
 <tr>
   <td><code>PRELD</code></td>
   <td>preload a specified number of bytes of data</td>
@@ -626,7 +626,7 @@
 <p>A normal load to register <code>GR0</code> prefetches data.
 The data prefetch instructions are [<a href="#ref_13">13</a>]:</p>
 
-<table class="padding5" border="1">
+<table class="border padding5">
 <tr><td><code>LDW</code></td><td>Prefetch cache line for read.</td></tr>
 <tr><td><code>LDD</code></td><td>Prefetch cache line for write.</td></tr>
 </table>
@@ -652,7 +652,7 @@
 <p>The PowerPC provides the following data prefetch instructions
 [<a href="#ref_14">14</a>]:</p>
 
-<table class="padding5" border="1">
+<table class="border padding5">
 <tr>
   <td>dcbt</td>
   <td>Data Cache Block Touch</td>
@@ -685,7 +685,7 @@
 [<a href="#ref_15">15</a>] instructions, whose variants are specified
 by the <em>fcn</em> field:</p>
 
-<table class="padding5" border="1">
+<table class="border padding5">
 <tr>
   <td>0</td>
   <td>prefetch for several reads</td>