[GCC][PATCH v2][Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bitmasks

[Sam Tebbs]

Hi James,

Thanks for the feedback. Here is an update with the changes you proposed 
and an updated changelog.

gcc/
2018-09-04  Sam Tebbs  <sam.tebbs@arm.com>

         PR target/85628
         * config/aarch64/aarch64.md (*aarch64_bfxil):
         Define.
         * config/aarch64/constraints.md (Ulc): Define
         * config/aarch64/aarch64-protos.h (aarch64_high_bits_all_ones_p):
         Define.
         * config/aarch64/aarch64.c (aarch64_high_bits_all_ones_p): New function.

gcc/testsuite
2018-09-04  Sam Tebbs  <sam.tebbs@arm.com>

         PR target/85628
         * gcc.target/aarch64/combine_bfxil.c: New file.
         * gcc.target/aarch64/combine_bfxil_2.c: New file.


On 08/28/2018 11:53 PM, James Greenhalgh wrote:
> Hm, I'm not very sure about the naming here; "left consecutive" isn't a
> common phrase to denote the mask you're looking for (exact_log2 (-i) != -1
> if I'm reading right), and is misleading 0x0000ffff is 'left consecutive'
> too, just with zeroes rather than ones.
>
>>   Â Â Â Â Â Â Â  * config/aarch64/aarch64.c (aarch64_is_left_consecutive):
>>           New function.
>>
>> gcc/testsuite
>> 2018-08-01Â  Sam Tebbs<sam.tebbs@arm.com>
>>
>>   Â Â Â Â Â Â Â  PR target/85628
>>   Â Â Â Â Â Â Â  * gcc.target/aarch64/combine_bfxil.c: New file.
>>   Â Â Â Â Â Â Â  * gcc.target/aarch64/combine_bfxil_2.c: New file.
>>
>>
>> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
>> index fa01475aa9ee579b6a3b2526295b622157120660..3cfa51b15af3e241672f1383cf881c12a44494a5 100644
>> --- a/gcc/config/aarch64/aarch64.c
>> +++ b/gcc/config/aarch64/aarch64.c
>> @@ -1454,6 +1454,14 @@ aarch64_hard_regno_caller_save_mode (unsigned regno, unsigned,
>>       return SImode;
>>   }
>>   
>> +/* Implement IS_LEFT_CONSECUTIVE.  Check if I's bits are consecutive
> What is IS_LEFT_CONSECUTIVE - I don't see it elsewhere in the GCC code, so
> what does the comment refer to implementing?
>
>> +   ones from the MSB.  */
>> +bool
>> +aarch64_is_left_consecutive (HOST_WIDE_INT i)
>> +{
>> +  return (i | (i - 1)) == HOST_WIDE_INT_M1;
> exact_log2(-i) != HOST_WIDE_INT_M1?

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