[PATCH][AArch64][3/3] Introduce mla64 type

[Kyrill Tkachov]

Hi all,

On some cores the X-register MADD/MSUB (and hence MUL and MNEG) instructions may behave differently
than the W-register forms and the scheduling models may want to reflect that.
That is currently not possible because both sizes use the mla scheduling type.

This patch introduces the mla64 type that is used to represent the 64-bit MADD,MSUB,MUL,MNEG instructions.
It annotates the necessary aarch64.md patterns and updates the existing aarch64 scheduling models to handle it.
It is currently handled the same way as the 32-bit forms so as not to introduce a difference in behaviour.
However, now we have the freedom to model it differently, if we so choose.
Sameera, Steve, Philipp, this is an FYI that you can update the relevant .md files to model these instructions
in a more precise way, if warranted (if this is approved.)

Bootstrapped and tested on aarch64-none-linux (and tested on arm-none-eabi).

Ok for trunk?

Thanks,
Kyrill

2018-11-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/arm/types.md (mla64): New type.
     * config/arm/xgene1.md: Handle mla64.
     * config/arm/cortex-a57.md: Likewise.
     * config/arm/cortex-a53.md: Likewise.
     * config/aarch64/thunderx2t99.md: Likewise.
     * config/aarch64/thunderx.md: Likewise.
     * config/aarch64/falkor.md: Likewise.
     * config/aarch64/saphira.md: Likewise.
     * config/aarch64/iterators.md (is_64_suf): New mode attribute.
     * config/aarch64/aarch64.md (mul<mode>3): Use is_64_suf in type.
     (madd<mode>): Likewise.
     (*msub<mode>): Likewise.
     (*mul<mode>_neg): Likewise.
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