Fix PR rtl-optimization/85925

[Eric Botcazou]

This is a regression present on all active branches: the combiner wrongly 
optimizes away a zero-extension on the ARM because it rewrites a ZERO_EXTRACT 
from SImode to HImode after having recorded that the upper bits of the results 
are cleared for WORD_REGISTER_OPERATIONS architectures.

I tried 3 approaches to fix the bug (with the help of Segher to evaluate the 
pessimization on various architectures):
 1. Disabling the WORD_REGISTER_OPERATIONS mechanism in the combiner,
 2. Preventing the ZERO_EXTRACT from being rewritten from SImode to HImode,
 3. Selectively disabling the WORD_REGISTER_OPERATIONS mechanism.

The 3 approaches pessimize (as expected) in the following order: 2 > 1 > 3.
The attached patch implements the 3rd approach, which seems a good compromise.

Tested on arm-elf and sparc-sun-solaris2.11, applied on all active branches.


2018-11-20  Eric Botcazou  <ebotcazou@adacore.com>

	PR rtl-optimization/85925
	* rtl.h (word_register_operation_p): New predicate.
	* combine.c (record_dead_and_set_regs_1): Only apply specific handling
	for WORD_REGISTER_OPERATIONS targets to word_register_operation_p RTX.
	* rtlanal.c (nonzero_bits1): Likewise.  Adjust couple of comments.
	(num_sign_bit_copies1): Likewise.


2018-11-20  Eric Botcazou  <ebotcazou@adacore.com>

	* gcc.c-torture/execute/20181120-1.c: New test.

-- 
Eric Botcazou
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