[RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #5

[Michael Meissner]

Patches #5..8 just add comments and reformat movd{f,d} constraints and
attributes so that it is a lot easier to tell which constraints and attributes
go together.  These do not (or at least should not) change the code generated.
Patch #9 does the same thing for mov{sf,sd} when floating point registers are
not available.

I have done both big and little endian bootstrap builds with all 5 patches
installed.  There were no regressions.

2018-03-22  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.md (mov<mode>_hardfloat32, FMOVE64):
	Reformat alternatives and attributes so it is easier to identify
	which constraints/attributes go with which instruction.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
-------------- next part --------------
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md	(revision 258719)
+++ gcc/config/rs6000/rs6000.md	(working copy)
@@ -7398,9 +7398,21 @@ (define_split
 ;; If we have FPR registers, rs6000_emit_move has moved all constants to memory,
 ;; except for 0.0 which can be created on VSX with an xor instruction.
 
+;;           STFD         LFD         FMR         LXSD        STXSD
+;;           LXSD         STXSD       XXLOR       XXLXOR      GPR<-0
+;;           LWZ          STW         MR
+
 (define_insn "*mov<mode>_hardfloat32"
-  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
-	(match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
+  [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
+            "=m,          d,          d,          <f64_p9>,   wY,
+              <f64_av>,   Z,          <f64_vsx>,  <f64_vsx>,  !r,
+              Y,          r,          !r")
+
+	(match_operand:FMOVE64 1 "input_operand"
+             "d,          m,          d,          wY,         <f64_p9>,
+              Z,          <f64_av>,   <f64_vsx>,  <zero_fp>,  <zero_fp>,
+              r,          Y,          r"))]
+
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT 
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7418,9 +7430,16 @@ (define_insn "*mov<mode>_hardfloat32"
    #
    #
    #"
-  [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,two,store,load,two")
+  [(set_attr "type"
+            "fpstore,     fpload,     fpsimple,   fpload,     fpstore,
+             fpload,      fpstore,    veclogical, veclogical, two,
+             store,       load,       two")
+
    (set_attr "size" "64")
-   (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8,8,8")])
+   (set_attr "length"
+            "4,           4,          4,          4,          4,
+             4,           4,          4,          4,          8,
+             8,           8,          8")])
 
 (define_insn "*mov<mode>_softfloat32"
   [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")