[PATCH], PowerPC long double transition patches, v2, Patch #2 (add missing conversion insn)

[Michael Meissner]

In reworking the ordering of the 128-bit floating point modes (June 18th, 2018
patch), I missed one conversion insn.  This meant the compiler would generate a
conversion to using the IF name.

I have tested this on a little endian power8 system with long double set to
IEEE 128-bit and IBM extended, and it fixes tests that convert between the
128-bit binary floating point types.  Can I install this on the trunk and back
port it to GCC 8.x?

[gcc]
2018-06-20  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.md (extendtfif2): Add missing 128-bit
	conversion insn.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797
-------------- next part --------------
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md	(revision 261602)
+++ gcc/config/rs6000/rs6000.md	(working copy)
@@ -8158,6 +8158,15 @@ (define_expand "extendtfkf2"
   DONE;
 })
 
+(define_expand "extendtfif2"
+  [(set (match_operand:IF 0 "gpc_reg_operand")
+	(float_extend:IF (match_operand:TF 1 "gpc_reg_operand")))]
+  "TARGET_FLOAT128_TYPE"
+{
+  rs6000_expand_float128_convert (operands[0], operands[1], false);
+  DONE;
+})
+
 (define_expand "trunciftf2"
   [(set (match_operand:TF 0 "gpc_reg_operand")
 	(float_truncate:TF (match_operand:IF 1 "gpc_reg_operand")))]