[PR83370][AARCH64]Use tighter register constraints for sibcall patterns.

[Renlin Li]

Hi Richard,

Thanks for the review!

On 29/01/18 20:23, Richard Sandiford wrote:
> 
> The patch looks good to me FWIW.  How about adding something like
> the following testcase?
> 
> ------------------------------------
> /* { dg-do run } */
> /* { dg-options "-O2" } */
> 
> typedef void (*fun) (void);
> 
> void __attribute__ ((noipa))
> f (fun x1)
> {
>    register fun x2 asm ("x16");
>    int arr[5000];
>    int *volatile ptr = arr;
>    asm ("mov %0, %1" : "=r" (x2) : "r" (x1));
>    x2 ();
> }
> 
> void g (void) {}
> 
> int
> main (void)
> {
>    f (g);
> }
> ------------------------------------

It was hard for me to construct an test case at that time.
Your example here exactly reflect the problem. The code-gen before the change is:

f:
	mov	x16, 20016
	sub	sp, sp, x16
	add	x0, sp, 16
	mov	x16, 20016
	str	x0, [sp, 8]
	add	sp, sp, x16
	br	x16

After the change to the register constraint:

f:
	mov	x16, 20016
	sub	sp, sp, x16
	// Start of user assembly
// 9 "indirect_tail_call_reg.c" 1
	mov x16, x0
// 0 "" 2
	// End of user assembly
	add	x0, sp, 16
	str	x0, [sp, 8]
	mov	x0, x16
	mov	x16, 20016
	add	sp, sp, x16
	br	x0

I updated the patch with the new test case,
the wording about the register constraint is also updated.

Thanks,
Renlin

gcc/ChangeLog:

2018-01-30  Renlin Li  <renlin.li@arm.com>

     * config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle
     TAILCALL_ADDR_REGS.
     (aarch64_register_move_cost): Likewise.
     * config/aarch64/aarch64.h (reg_class): Rename CALLER_SAVE_REGS to
     TAILCALL_ADDR_REGS.
     (REG_CLASS_NAMES): Likewise.
     (REG_CLASS_CONTENTS): Rename CALLER_SAVE_REGS to
     TAILCALL_ADDR_REGS. Remove IP registers.
     * config/aarch64/aarch64.md (Ucs): Update register constraint.

gcc/testsuite/ChangeLog:

2018-01-30  Richard Sandiford  <richard.sandiford@linaro.org>

     * gcc.target/aarch64/indirect_tail_call_reg.c: New.

> 
>> [...]
>> diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
>> index af4143ef756464afac29d17f124b436520f90451..c3791aa89562a5d5542098d2f7951afc57901150 100644
>> --- a/gcc/config/aarch64/constraints.md
>> +++ b/gcc/config/aarch64/constraints.md
>> @@ -21,8 +21,8 @@
>>   (define_register_constraint "k" "STACK_REG"
>>     "@internal The stack register.")
>>   
>> -(define_register_constraint "Ucs" "CALLER_SAVE_REGS"
>> -  "@internal The caller save registers.")
>> +(define_register_constraint "Ucs" "TAILCALL_ADDR_REGS"
>> +  "@internal The indirect tail call address registers")
>>   
>>   (define_register_constraint "w" "FP_REGS"
>>     "Floating point and SIMD vector registers.")
> 
> Maybe "@internal Registers suitable for an indirect tail call"?
> Unlike the caller-save registers, these aren't a predefined set.
> 
> Thanks,
> Richard
> 
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