[AARCH64] Neon vld1_*_x3, vst1_*_x2 and vst1_*_x3 intrinsics
Sameera Deshpande
sameera.deshpande@linaro.org
Wed Apr 11 08:04:00 GMT 2018
On 10 April 2018 at 20:07, Sudakshina Das <sudi.das@arm.com> wrote:
> Hi Sameera
>
>
> On 10/04/18 11:20, Sameera Deshpande wrote:
>>
>> On 7 April 2018 at 01:25, Christophe Lyon <christophe.lyon@linaro.org>
>> wrote:
>>>
>>> Hi,
>>>
>>> 2018-04-06 12:15 GMT+02:00 Sameera Deshpande
>>> <sameera.deshpande@linaro.org>:
>>>>
>>>> Hi Christophe,
>>>>
>>>> Please find attached the updated patch with testcases.
>>>>
>>>> Ok for trunk?
>>>
>>>
>>> Thanks for the update.
>>>
>>> Since the new intrinsics are only available on aarch64, you want to
>>> prevent the tests from running on arm.
>>> Indeed gcc.target/aarch64/advsimd-intrinsics/ is shared between the two
>>> targets.
>>> There are several examples on how to do that in that directory.
>>>
>>> I have also noticed that the tests fail at execution on aarch64_be.
>>>
>>> I didn't look at the patch in details.
>>>
>>> Christophe
>>>
>>>
>>>>
>>>> - Thanks and regards,
>>>> Sameera D.
>>>>
>>>> 2017-12-14 22:17 GMT+05:30 Christophe Lyon <christophe.lyon@linaro.org>:
>>>>>
>>>>> 2017-12-14 9:29 GMT+01:00 Sameera Deshpande
>>>>> <sameera.deshpande@linaro.org>:
>>>>>>
>>>>>> Hi!
>>>>>>
>>>>>> Please find attached the patch implementing vld1_*_x3, vst1_*_x2 and
>>>>>> vst1_*_x3 intrinsics as defined by Neon document.
>>>>>>
>>>>>> Ok for trunk?
>>>>>>
>>>>>> - Thanks and regards,
>>>>>> Sameera D.
>>>>>>
>>>>>> gcc/Changelog:
>>>>>>
>>>>>> 2017-11-14 Sameera Deshpande <sameera.deshpande@linaro.org>
>>>>>>
>>>>>>
>>>>>> * config/aarch64/aarch64-simd-builtins.def (ld1x3): New.
>>>>>> (st1x2): Likewise.
>>>>>> (st1x3): Likewise.
>>>>>> * config/aarch64/aarch64-simd.md
>>>>>> (aarch64_ld1x3<VALLDIF:mode>): New pattern.
>>>>>> (aarch64_ld1_x3_<mode>): Likewise
>>>>>> (aarch64_st1x2<VALLDIF:mode>): Likewise
>>>>>> (aarch64_st1_x2_<mode>): Likewise
>>>>>> (aarch64_st1x3<VALLDIF:mode>): Likewise
>>>>>> (aarch64_st1_x3_<mode>): Likewise
>>>>>> * config/aarch64/arm_neon.h (vld1_u8_x3): New function.
>>>>>> (vld1_s8_x3): Likewise.
>>>>>> (vld1_u16_x3): Likewise.
>>>>>> (vld1_s16_x3): Likewise.
>>>>>> (vld1_u32_x3): Likewise.
>>>>>> (vld1_s32_x3): Likewise.
>>>>>> (vld1_u64_x3): Likewise.
>>>>>> (vld1_s64_x3): Likewise.
>>>>>> (vld1_fp16_x3): Likewise.
>>>>>> (vld1_f32_x3): Likewise.
>>>>>> (vld1_f64_x3): Likewise.
>>>>>> (vld1_p8_x3): Likewise.
>>>>>> (vld1_p16_x3): Likewise.
>>>>>> (vld1_p64_x3): Likewise.
>>>>>> (vld1q_u8_x3): Likewise.
>>>>>> (vld1q_s8_x3): Likewise.
>>>>>> (vld1q_u16_x3): Likewise.
>>>>>> (vld1q_s16_x3): Likewise.
>>>>>> (vld1q_u32_x3): Likewise.
>>>>>> (vld1q_s32_x3): Likewise.
>>>>>> (vld1q_u64_x3): Likewise.
>>>>>> (vld1q_s64_x3): Likewise.
>>>>>> (vld1q_f16_x3): Likewise.
>>>>>> (vld1q_f32_x3): Likewise.
>>>>>> (vld1q_f64_x3): Likewise.
>>>>>> (vld1q_p8_x3): Likewise.
>>>>>> (vld1q_p16_x3): Likewise.
>>>>>> (vld1q_p64_x3): Likewise.
>>>>>> (vst1_s64_x2): Likewise.
>>>>>> (vst1_u64_x2): Likewise.
>>>>>> (vst1_f64_x2):
>>>>>> Likewise.patchurl=http://people.linaro.org/~christophe.lyon/armv8_2-fp16-scalar-2.patch3
>>>
>>> patchname=armv8_2-fp16-scalar-2.patch3
>>> refrev=259064
>>> email_to=christophe.lyon@linaro.org
>>>
>>>>>> (vst1_s8_x2): Likewise.
>>>>>> (vst1_p8_x2): Likewise.
>>>>>> (vst1_s16_x2): Likewise.
>>>>>> (vst1_p16_x2): Likewise.
>>>>>> (vst1_s32_x2): Likewise.
>>>>>> (vst1_u8_x2): Likewise.
>>>>>> (vst1_u16_x2): Likewise.
>>>>>> (vst1_u32_x2): Likewise.
>>>>>> (vst1_f16_x2): Likewise.
>>>>>> (vst1_f32_x2): Likewise.
>>>>>> (vst1_p64_x2): Likewise.
>>>>>> (vst1q_s8_x2): Likewise.
>>>>>> (vst1q_p8_x2): Likewise.
>>>>>> (vst1q_s16_x2): Likewise.
>>>>>> (vst1q_p16_x2): Likewise.
>>>>>> (vst1q_s32_x2): Likewise.
>>>>>> (vst1q_s64_x2): Likewise.
>>>>>> (vst1q_u8_x2): Likewise.
>>>>>> (vst1q_u16_x2): Likewise.
>>>>>> (vst1q_u32_x2): Likewise.
>>>>>> (vst1q_u64_x2): Likewise.
>>>>>> (vst1q_f16_x2): Likewise.
>>>>>> (vst1q_f32_x2): Likewise.
>>>>>> (vst1q_f64_x2): Likewise.
>>>>>> (vst1q_p64_x2): Likewise.
>>>>>> (vst1_s64_x3): Likewise.
>>>>>> (vst1_u64_x3): Likewise.
>>>>>> (vst1_f64_x3): Likewise.
>>>>>> (vst1_s8_x3): Likewise.
>>>>>> (vst1_p8_x3): Likewise.
>>>>>> (vst1_s16_x3): Likewise.
>>>>>> (vst1_p16_x3): Likewise.
>>>>>> (vst1_s32_x3): Likewise.
>>>>>> (vst1_u8_x3): Likewise.
>>>>>> (vst1_u16_x3): Likewise.
>>>>>> (vst1_u32_x3): Likewise.
>>>>>> (vst1_f16_x3): Likewise.
>>>>>> (vst1_f32_x3): Likewise.
>>>>>> (vst1_p64_x3): Likewise.
>>>>>> (vst1q_s8_x3): Likewise.
>>>>>> (vst1q_p8_x3): Likewise.
>>>>>> (vst1q_s16_x3): Likewise.
>>>>>> (vst1q_p16_x3): Likewise.
>>>>>> (vst1q_s32_x3): Likewise.
>>>>>> (vst1q_s64_x3): Likewise.
>>>>>> (vst1q_u8_x3): Likewise.
>>>>>> (vst1q_u16_x3): Likewise.
>>>>>> (vst1q_u32_x3): Likewise.
>>>>>> (vst1q_u64_x3): Likewise.
>>>>>> (vst1q_f16_x3): Likewise.
>>>>>> (vst1q_f32_x3): Likewise.
>>>>>> (vst1q_f64_x3): Likewise.
>>>>>> (vst1q_p64_x3): Likewise.
>>>>>
>>>>>
>>>>> Hi,
>>>>> I'm not a maintainer, but I suspect you should add some tests.
>>>>>
>>>>> Christophe
>>>>
>>>>
>>>>
>>>>
>>>> --
>>>> - Thanks and regards,
>>>> Sameera D.
>>
>>
>> Hi Christophe,
>>
>> Please find attached the updated patch. Similar to the testcase
>> vld1x2.c, I have updated the testcases to mark them XFAIL for ARM, as
>> the intrinsics are not implemented yet. I have also added required
>> target to be little endian.
>
>
> I am not a maintainer either. Shouldn't these intrinsics be supported
> even for big endian?
>
Yes, they should be implemented, however it is out of scope of this patch.
> From your patch:
>
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c
>
> new file mode 100644
> index 0000000..c37c72c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c
> @@ -0,0 +1,82 @@
> +/* We haven't implemented these intrinsics for arm yet. */
> +/* { dg-xfail-if "" { arm*-*-* } } */
> +/* { dg-require-effective-target aarch64_little_endian } */
>
> According to
> https://gcc.gnu.org/onlinedocs/gccint/Directives.html#Skip-a-test-for-some-targets
> this must follow the dg-do directive.
>
> Also I think the require-effective-target directive will only allow
> the test to run on aarch64-*-*-* so the xfail on arm-*-*-* is kind
> of not helpful. Maybe something like:
>
> /* { dg-require-effective-target aarch64_little_endian { target {
> aarch64*-*-* } } } */
Ok, then I will restrict this test only for aarch64_little_endian, as
that is the purpose of this test.
>
> So that the check is not performed on arm-*-*-* and the test runs
> and fails and then the xfail makes more sense.
>
> In case the big endian version is also expected to be implemented
> in the future, something like:
>
> /* { dg-xfail-if "" { arm*-*-* || aarch64_big_endian } } */
>
> or
>
> /* { dg-do run { xfail { arm*-*-* || aarch64_big_endian } } } */
>
> would be simpler. (PS: I haven't tested any of these directive myself).
>
Please find attached updated patch.
>
> Thanks
> Sudi
>
>
> +/* { dg-do run } */
> +/* { dg-options "-O3" } */
>
>
>
>> Ok for thrunk?
>>
>> - Thanks and regards,
>> Sameera D.
>>
>> gcc/Changelog:
>>
>> 2018-04-10 Sameera Deshpande <sameera.deshpande@linaro.org>
>>
>>
>> * config/aarch64/aarch64-simd-builtins.def (ld1x3): New.
>> (st1x2): Likewise.
>> (st1x3): Likewise.
>> * config/aarch64/aarch64-simd.md
>> (aarch64_ld1x3<VALLDIF:mode>): New pattern.
>> (aarch64_ld1_x3_<mode>): Likewise
>> (aarch64_st1x2<VALLDIF:mode>): Likewise
>> (aarch64_st1_x2_<mode>): Likewise
>> (aarch64_st1x3<VALLDIF:mode>): Likewise
>> (aarch64_st1_x3_<mode>): Likewise
>> * config/aarch64/arm_neon.h (vld1_u8_x3): New function.
>> (vld1_s8_x3): Likewise.
>> (vld1_u16_x3): Likewise.
>> (vld1_s16_x3): Likewise.
>> (vld1_u32_x3): Likewise.
>> (vld1_s32_x3): Likewise.
>> (vld1_u64_x3): Likewise.
>> (vld1_s64_x3): Likewise.
>> (vld1_f16_x3): Likewise.
>> (vld1_f32_x3): Likewise.
>> (vld1_f64_x3): Likewise.
>> (vld1_p8_x3): Likewise.
>> (vld1_p16_x3): Likewise.
>> (vld1_p64_x3): Likewise.
>> (vld1q_u8_x3): Likewise.
>> (vld1q_s8_x3): Likewise.
>> (vld1q_u16_x3): Likewise.
>> (vld1q_s16_x3): Likewise.
>> (vld1q_u32_x3): Likewise.
>> (vld1q_s32_x3): Likewise.
>> (vld1q_u64_x3): Likewise.
>> (vld1q_s64_x3): Likewise.
>> (vld1q_f16_x3): Likewise.
>> (vld1q_f32_x3): Likewise.
>> (vld1q_f64_x3): Likewise.
>> (vld1q_p8_x3): Likewise.
>> (vld1q_p16_x3): Likewise.
>> (vld1q_p64_x3): Likewise.
>> (vst1_s64_x2): Likewise.
>> (vst1_u64_x2): Likewise.
>> (vst1_f64_x2): Likewise.
>> (vst1_s8_x2): Likewise.
>> (vst1_p8_x2): Likewise.
>> (vst1_s16_x2): Likewise.
>> (vst1_p16_x2): Likewise.
>> (vst1_s32_x2): Likewise.
>> (vst1_u8_x2): Likewise.
>> (vst1_u16_x2): Likewise.
>> (vst1_u32_x2): Likewise.
>> (vst1_f16_x2): Likewise.
>> (vst1_f32_x2): Likewise.
>> (vst1_p64_x2): Likewise.
>> (vst1q_s8_x2): Likewise.
>> (vst1q_p8_x2): Likewise.
>> (vst1q_s16_x2): Likewise.
>> (vst1q_p16_x2): Likewise.
>> (vst1q_s32_x2): Likewise.
>> (vst1q_s64_x2): Likewise.
>> (vst1q_u8_x2): Likewise.
>> (vst1q_u16_x2): Likewise.
>> (vst1q_u32_x2): Likewise.
>> (vst1q_u64_x2): Likewise.
>> (vst1q_f16_x2): Likewise.
>> (vst1q_f32_x2): Likewise.
>> (vst1q_f64_x2): Likewise.
>> (vst1q_p64_x2): Likewise.
>> (vst1_s64_x3): Likewise.
>> (vst1_u64_x3): Likewise.
>> (vst1_f64_x3): Likewise.
>> (vst1_s8_x3): Likewise.
>> (vst1_p8_x3): Likewise.
>> (vst1_s16_x3): Likewise.
>> (vst1_p16_x3): Likewise.
>> (vst1_s32_x3): Likewise.
>> (vst1_u8_x3): Likewise.
>> (vst1_u16_x3): Likewise.
>> (vst1_u32_x3): Likewise.
>> (vst1_f16_x3): Likewise.
>> (vst1_f32_x3): Likewise.
>> (vst1_p64_x3): Likewise.
>> (vst1q_s8_x3): Likewise.
>> (vst1q_p8_x3): Likewise.
>> (vst1q_s16_x3): Likewise.
>> (vst1q_p16_x3): Likewise.
>> (vst1q_s32_x3): Likewise.
>> (vst1q_s64_x3): Likewise.
>> (vst1q_u8_x3): Likewise.
>> (vst1q_u16_x3): Likewise.
>> (vst1q_u32_x3): Likewise.
>> (vst1q_u64_x3): Likewise.
>> (vst1q_f16_x3): Likewise.
>> (vst1q_f32_x3): Likewise.
>> (vst1q_f64_x3): Likewise.
>> (vst1q_p64_x3): Likewise.
>>
>> gcc/testsuite/Changelog:
>>
>> 2018-04-10 Sameera Deshpande <sameera.deshpande@linaro.org>
>>
>> * gcc.target/aarch64/advsimd-intrinsics/vld1x3.c: New test for
>> vld1x3 intrinsics for aarch64_little_endian.
>> * gcc.target/aarch64/advsimd-intrinsics/vst1x2.c: New test for
>> vst1x2 intrinsics for aarch64_little_endian.
>> * gcc.target/aarch64/advsimd-intrinsics/vst1x3.c: New test for
>> vst1x3 intrinsics for aarch64_little_endian.
>>
>
--
- Thanks and regards,
Sameera D.
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