[PATCH], Improve moving SFmode to GPR on PowerPC, #2 of 8

[Michael Meissner]

On Tue, Sep 26, 2017 at 11:06:09AM -0500, Segher Boessenkool wrote:
> > @@ -6850,52 +6850,41 @@ (define_insn_and_split "movsi_from_sf"
> >    rtx op1 = operands[1];
> >    rtx op2 = operands[2];
> >    rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
> > +  rtx op2_si = gen_rtx_REG (SImode, REGNO (op2));
> >  
> 
> Does this work, btw?  I would expect you need reg_or_subregno, for op0
> that is (the new op2 might be fine, not sure).  You do use it in most
> places; please check.

It does work, but using reg_or_subreno is better.  I've changed it.

> >  ;; movsi_from_sf with zero extension
> >  ;;
> >  ;;		RLDICL       LWZ          LFIWZX       LXSIWZX   VSX->GPR
> > -;;		MTVSRWZ      VSX->VSX
> > +;;		VSX->VSX     MTVSRWZ
> >  
> >  (define_insn_and_split "*movdi_from_sf_zero_ext"
> >    [(set (match_operand:DI 0 "gpc_reg_operand"
> >  		"=r,         r,           ?*wI,        ?*wH,     r,
> > -		wIwH,        ?wK")
> > +		 wK,         wIwH")
> 
> This loses the "?", is that on purpose?

No.  I'll put it back (but I do think it is harmless, since the direct move
occurs before it).  In my original patches, I just left the value in a vector
register, and let the register allocator generate the direct move.  However,
when I updated the peephole2 (patch #7), it was a lot easier to write, if I
kept in the direct move option.  But I missed putting the '?' back in.
Thanks.

> >    [(set_attr "type"
> >  		"*,          load,        fpload,      fpload,  mftgpr,
> > -		 mffgpr,     veclogical")
> > +		 vecexts,    mffgpr")
> 
> vecsimple or vecfloat I guess, not vecexts.  We have no way of describing
> it exactly, of course.  Maybe just "two".

Ok.

> Okay for trunk with those things taken care of.  Thanks!

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797