[PATCH] RISC-V: Fix build error
Palmer Dabbelt
palmer@sifive.com
Wed Nov 8 22:26:00 GMT 2017
Committed. Thanks, Kito :).
On Tue, 07 Nov 2017 15:20:05 PST (-0800), Palmer Dabbelt wrote:
> From: Kito Cheng <kito.cheng@gmail.com>
>
> - This build error was indroduced by "RISC-V: Implement movmemsi"
> and "RISC-V: Support -mpreferred-stack-boundary flag"
>
> gcc/ChangeLog
>
> 2017-11-07 Kito Cheng <kito.cheng@gmail.com>
>
> * config/riscv/riscv-protos.h (riscv_slow_unaligned_access_p):
> New extern.
> (MOVE_RATIO): Use riscv_slow_unaligned_access_p.
> config/riscv/riscv.c (predict.h): New include.
> (riscv_slow_unaligned_access_p): No longer static.
> (riscv_block_move_straight): Add require.
> config/riscv/riscv-protos.h (riscv_hard_regno_nregs): Delete.
> ---
> gcc/config/riscv/riscv-protos.h | 1 -
> gcc/config/riscv/riscv.c | 5 +++--
> gcc/config/riscv/riscv.h | 4 +++-
> 3 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 34f9859928e2..5f65b20e792e 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -68,7 +68,6 @@ extern void riscv_expand_prologue (void);
> extern void riscv_expand_epilogue (bool);
> extern bool riscv_can_use_return_insn (void);
> extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
> -extern unsigned int riscv_hard_regno_nregs (int, enum machine_mode);
> extern bool riscv_expand_block_move (rtx, rtx, rtx);
>
> /* Routines implemented in riscv-c.c. */
> diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
> index e9783e920ef6..279af909a694 100644
> --- a/gcc/config/riscv/riscv.c
> +++ b/gcc/config/riscv/riscv.c
> @@ -51,6 +51,7 @@ along with GCC; see the file COPYING3. If not see
> #include "df.h"
> #include "diagnostic.h"
> #include "builtins.h"
> +#include "predict.h"
>
> /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
> #define UNSPEC_ADDRESS_P(X) \
> @@ -217,7 +218,7 @@ struct riscv_cpu_info {
> /* Global variables for machine-dependent things. */
>
> /* Whether unaligned accesses execute very slowly. */
> -static bool riscv_slow_unaligned_access_p;
> +bool riscv_slow_unaligned_access_p;
>
> /* Which tuning parameters to use. */
> static const struct riscv_tune_info *tune_info;
> @@ -2657,7 +2658,7 @@ riscv_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
> bits = MAX (BITS_PER_UNIT,
> MIN (BITS_PER_WORD, MIN (MEM_ALIGN (src), MEM_ALIGN (dest))));
>
> - mode = mode_for_size (bits, MODE_INT, 0);
> + mode = mode_for_size (bits, MODE_INT, 0).require ();
> delta = bits / BITS_PER_UNIT;
>
> /* Allocate a buffer for the temporary registers. */
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index c0901a093033..91a9c33543d2 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -824,7 +824,7 @@ while (0)
> case, movmem or libcall is more efficient. */
>
> #define MOVE_RATIO(speed) \
> - (!STRICT_ALIGNMENT && riscv_slow_unaligned_access ? 1 : \
> + (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 : \
> (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD : \
> CLEAR_RATIO (speed) / 2)
>
> @@ -841,6 +841,8 @@ while (0)
>
> #ifndef USED_FOR_TARGET
> extern const enum reg_class riscv_regno_to_class[];
> +extern bool riscv_slow_unaligned_access_p;
> +extern unsigned riscv_stack_boundary;
> #endif
>
> #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
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