[PATCH, GCC/ARM, Stage 1] Enable Purecode for ARMv8-M Baseline

Christophe Lyon christophe.lyon@linaro.org
Tue May 9 16:28:00 GMT 2017


Hi,


On 4 May 2017 at 11:05, Ramana Radhakrishnan
<ramana.radhakrishnan@arm.com> wrote:
> On Thu, May 04, 2017 at 09:50:42AM +0100, Prakhar Bahuguna wrote:
> <unnecessary bits snipped>
>
>> >
>> > Otherwise ok. Please respin and test with an armhf thumb32 bootstrap
>> > and regression test run.
>> >
>> > regards
>> > Ramana
>>
>> I've respun this patch with the suggested changes, along with a new changelog
>> for docs:
>
> And tested hopefully with a bootstrap and regression test run on armhf on
> GNU/Linux ?
>
> Ok if no regressions.
>

I've noticed regressions :(

  - PASS now FAIL             [PASS => FAIL]:
  Executed from: gcc.target/arm/arm.exp
    gcc.target/arm/scd42-2.c scan-assembler mov[ \t].*272
on arm* targets generating arm code as opposed to thumb

and in g++:
  Executed from: g++.dg/torture/dg-torture.exp
    g++.dg/torture/vshuf-v4si.C   -O2  (internal compiler error)
    g++.dg/torture/vshuf-v4si.C   -O2 -flto -fno-use-linker-plugin
-flto-partition=none  (internal compiler error)
    g++.dg/torture/vshuf-v4si.C   -O2 -flto -fuse-linker-plugin
-fno-fat-lto-objects  (internal compiler error)

when using -march=armv5t or using the default cpu/fpu/mode settings.

For more details, see:
http://people.linaro.org/~christophe.lyon/cross-validation/gcc/trunk/247585/report-build-info.html

Thanks,

Christophe

> regards
> Ramana
>
>>
>> doc/ChangeLog:
>>
>> 2017-01-11  Prakhar Bahuguna  <prakhar.bahuguna@arm.com>
>>           Andre Simoes Dias Vieira  <andre.simoesdiasvieira@arm.com>
>>
>>       * invoke.texi (-mpure-code): Change "ARMv7-M targets" for
>>       "M-profile targets with the MOVT instruction".
>>
>> --
>>
>> Prakhar Bahuguna
>
>> From e0f62c9919ceb9cfc6b4cc49615fb7188ae50519 Mon Sep 17 00:00:00 2001
>> From: Prakhar Bahuguna <prakhar.bahuguna@arm.com>
>> Date: Wed, 15 Mar 2017 10:25:03 +0000
>> Subject: [PATCH] Enable Purecode for ARMv8-M Baseline.
>>
>> ---
>>  gcc/config/arm/arm.c                               | 78 ++++++++++++++--------
>>  gcc/config/arm/arm.md                              |  6 +-
>>  gcc/doc/invoke.texi                                |  3 +-
>>  .../gcc.target/arm/pure-code/pure-code.exp         |  5 +-
>>  4 files changed, 58 insertions(+), 34 deletions(-)
>>
>> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
>> index 83914913433..e0a7cabcb2e 100644
>> --- a/gcc/config/arm/arm.c
>> +++ b/gcc/config/arm/arm.c
>> @@ -2833,16 +2833,16 @@ arm_option_check_internal (struct gcc_options *opts)
>>        flag_pic = 0;
>>      }
>>
>> -  /* We only support -mslow-flash-data on armv7-m targets.  */
>> -  if (target_slow_flash_data
>> -      && ((!(arm_arch7 && !arm_arch_notm) && !arm_arch7em)
>> -       || (TARGET_THUMB1_P (flags) || flag_pic || TARGET_NEON)))
>> -    error ("-mslow-flash-data only supports non-pic code on armv7-m targets");
>> -
>> -  /* We only support pure-code on Thumb-2 M-profile targets.  */
>> -  if (target_pure_code
>> -      && (!arm_arch_thumb2 || arm_arch_notm || flag_pic || TARGET_NEON))
>> -    error ("-mpure-code only supports non-pic code on armv7-m targets");
>> +  /* We only support -mpure-code and -mslow-flash-data on M-profile targets
>> +     with MOVT.  */
>> +  if ((target_pure_code || target_slow_flash_data)
>> +      && (!TARGET_HAVE_MOVT || arm_arch_notm || flag_pic || TARGET_NEON))
>> +    {
>> +      const char *flag = (target_pure_code ? "-mpure-code" :
>> +                                          "-mslow-flash-data");
>> +      error ("%s only supports non-pic code on M-profile targets with the "
>> +          "MOVT instruction", flag);
>> +    }
>>
>>  }
>>
>> @@ -4077,7 +4077,7 @@ const_ok_for_arm (HOST_WIDE_INT i)
>>              || (i & ~0xfc000003) == 0))
>>       return TRUE;
>>      }
>> -  else
>> +  else if (TARGET_THUMB2)
>>      {
>>        HOST_WIDE_INT v;
>>
>> @@ -4093,6 +4093,14 @@ const_ok_for_arm (HOST_WIDE_INT i)
>>        if (i == v)
>>       return TRUE;
>>      }
>> +  else if (TARGET_HAVE_MOVT)
>> +    {
>> +      /* Thumb-1 Targets with MOVT.  */
>> +      if (i > 0xffff)
>> +     return FALSE;
>> +      else
>> +     return TRUE;
>> +    }
>>
>>    return FALSE;
>>  }
>> @@ -7736,6 +7744,32 @@ arm_legitimate_address_outer_p (machine_mode mode, rtx x, RTX_CODE outer,
>>    return 0;
>>  }
>>
>> +/* Return true if we can avoid creating a constant pool entry for x.  */
>> +static bool
>> +can_avoid_literal_pool_for_label_p (rtx x)
>> +{
>> +  /* Normally we can assign constant values to target registers without
>> +     the help of constant pool.  But there are cases we have to use constant
>> +     pool like:
>> +     1) assign a label to register.
>> +     2) sign-extend a 8bit value to 32bit and then assign to register.
>> +
>> +     Constant pool access in format:
>> +     (set (reg r0) (mem (symbol_ref (".LC0"))))
>> +     will cause the use of literal pool (later in function arm_reorg).
>> +     So here we mark such format as an invalid format, then the compiler
>> +     will adjust it into:
>> +     (set (reg r0) (symbol_ref (".LC0")))
>> +     (set (reg r0) (mem (reg r0))).
>> +     No extra register is required, and (mem (reg r0)) won't cause the use
>> +     of literal pools.  */
>> +  if (arm_disable_literal_pool && GET_CODE (x) == SYMBOL_REF
>> +      && CONSTANT_POOL_ADDRESS_P (x))
>> +    return 1;
>> +  return 0;
>> +}
>> +
>> +
>>  /* Return nonzero if X is a valid Thumb-2 address operand.  */
>>  static int
>>  thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
>> @@ -7799,23 +7833,7 @@ thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
>>                 && thumb2_legitimate_index_p (mode, xop0, strict_p)));
>>      }
>>
>> -  /* Normally we can assign constant values to target registers without
>> -     the help of constant pool.  But there are cases we have to use constant
>> -     pool like:
>> -     1) assign a label to register.
>> -     2) sign-extend a 8bit value to 32bit and then assign to register.
>> -
>> -     Constant pool access in format:
>> -     (set (reg r0) (mem (symbol_ref (".LC0"))))
>> -     will cause the use of literal pool (later in function arm_reorg).
>> -     So here we mark such format as an invalid format, then the compiler
>> -     will adjust it into:
>> -     (set (reg r0) (symbol_ref (".LC0")))
>> -     (set (reg r0) (mem (reg r0))).
>> -     No extra register is required, and (mem (reg r0)) won't cause the use
>> -     of literal pools.  */
>> -  else if (arm_disable_literal_pool && code == SYMBOL_REF
>> -        && CONSTANT_POOL_ADDRESS_P (x))
>> +  else if (can_avoid_literal_pool_for_label_p (x))
>>      return 0;
>>
>>    else if (GET_MODE_CLASS (mode) != MODE_FLOAT
>> @@ -8094,6 +8112,9 @@ thumb1_index_register_rtx_p (rtx x, int strict_p)
>>  int
>>  thumb1_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
>>  {
>> +  if (TARGET_HAVE_MOVT && can_avoid_literal_pool_for_label_p (x))
>> +    return 0;
>> +
>>    /* ??? Not clear if this is right.  Experiment.  */
>>    if (GET_MODE_SIZE (mode) < 4
>>        && !(reload_in_progress || reload_completed)
>> @@ -8706,6 +8727,7 @@ thumb_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
>>    return (CONST_INT_P (x)
>>         || CONST_DOUBLE_P (x)
>>         || CONSTANT_ADDRESS_P (x)
>> +       || (TARGET_HAVE_MOVT && GET_CODE (x) == SYMBOL_REF)
>>         || flag_pic);
>>  }
>>
>> diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
>> index 21cfe3a4c31..d50059b28ab 100644
>> --- a/gcc/config/arm/arm.md
>> +++ b/gcc/config/arm/arm.md
>> @@ -5972,7 +5972,7 @@
>>    {
>>    rtx base, offset, tmp;
>>
>> -  if (TARGET_32BIT)
>> +  if (TARGET_HAVE_MOVT)
>>      {
>>        /* Everything except mem = const or mem = mem can be done easily.  */
>>        if (MEM_P (operands[0]))
>> @@ -5996,7 +5996,7 @@
>>            }
>>          }
>>      }
>> -  else /* TARGET_THUMB1...  */
>> +  else /* Target doesn't have MOVT...  */
>>      {
>>        if (can_create_pseudo_p ())
>>          {
>> @@ -6096,7 +6096,7 @@
>>  (define_split
>>    [(set (match_operand:SI 0 "arm_general_register_operand" "")
>>       (match_operand:SI 1 "const_int_operand" ""))]
>> -  "TARGET_32BIT
>> +  "TARGET_HAVE_MOVT
>>    && (!(const_ok_for_arm (INTVAL (operands[1]))
>>          || const_ok_for_arm (~INTVAL (operands[1]))))"
>>    [(clobber (const_int 0))]
>> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
>> index 438e553b340..68a558e9992 100644
>> --- a/gcc/doc/invoke.texi
>> +++ b/gcc/doc/invoke.texi
>> @@ -15421,7 +15421,8 @@ by default.
>>  Do not allow constant data to be placed in code sections.
>>  Additionally, when compiling for ELF object format give all text sections the
>>  ELF processor-specific section attribute @code{SHF_ARM_PURECODE}.  This option
>> -is only available when generating non-pic code for ARMv7-M targets.
>> +is only available when generating non-pic code for M-profile targets with the
>> +MOVT instruction.
>>
>>  @item -mcmse
>>  @opindex mcmse
>> diff --git a/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp b/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp
>> index 6a5dc552bf3..a5109231926 100644
>> --- a/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp
>> +++ b/gcc/testsuite/gcc.target/arm/pure-code/pure-code.exp
>> @@ -26,8 +26,9 @@ if ![info exists DEFAULT_CFLAGS] then {
>>  }
>>
>>  # The -mpure-code option is only available for M-profile targets that support
>> -# thumb2.
>> -if {[check_effective_target_arm_thumb2_ok]
>> +# the MOVT instruction.
>> +if {([check_effective_target_arm_thumb2_ok]
>> +     || [check_effective_target_arm_thumb1_movt_ok])
>>      && [check_effective_target_arm_cortex_m]} then {
>>  # Initialize `dg'.
>>  dg-init
>> --
>> 2.11.0
>>
>



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