[PATCH,RS6000] PR79963: Correct which condition code bit represents result of vec_any_eq built-in function

[Kelvin Nilsen]

This patch corrects several errors in a patch that was submitted on
2017-03-01.  A copy-and-paste error in the previous patch resulted in
accidental use of the lt flag instead of the eq flag to represent the
outcome of the vec_any_eq built-in function.  Also, in reviewing the
code of the previous patch, it was discovered that changes to the C++
templates representing the vec_all_ne and vec_any_eq built-in functions
were incomplete.

This patch has bootstrapped and been tested on
powerpc64le-unknown-linux with no regressions.

Is this ok for trunk?

gcc/ChangeLog:

2017-03-14  Kelvin Nilsen  <kelvin@gcc.gnu.org>

	PR target/79963
	* config/rs6000/altivec.h (vec_all_ne): Under __cplusplus++ and
	__POWER9_VECTOR__ #ifdef control, change template definition to
	use Power9-specific built-in function.
	(vec_any_eq): Likewise.
	* config/rs6000/vector.md (vector_ae_v2di_p): Change the flag used
	to control outcomes from this test.
	(vector_ae_<mode>p): For VEC_F modes, likewise.

Index: gcc/config/rs6000/altivec.h
===================================================================
--- gcc/config/rs6000/altivec.h	(revision 246096)
+++ gcc/config/rs6000/altivec.h	(working copy)
@@ -521,9 +521,9 @@ __altivec_scalar_pred(vec_all_nez,
 __altivec_scalar_pred(vec_any_eqz,
   __builtin_vec_vcmpnez_p (__CR6_LT_REV, a1, a2))
 __altivec_scalar_pred(vec_all_ne,
-  __builtin_vec_allne_p (a1, a2))
+  __builtin_vec_vcmpne_p (a1, a2))
 __altivec_scalar_pred(vec_any_eq,
-  __builtin_vec_anyeq_p (a1, a2))
+  __builtin_vec_vcmpae_p (a1, a2))
 #endif
 
 __altivec_scalar_pred(vec_any_ne,
Index: gcc/config/rs6000/vector.md
===================================================================
--- gcc/config/rs6000/vector.md	(revision 246096)
+++ gcc/config/rs6000/vector.md	(working copy)
@@ -790,7 +790,7 @@
 	  (eq:V2DI (match_dup 1)
 		   (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(lt:SI (reg:CC CR6_REGNO)
+	(eq:SI (reg:CC CR6_REGNO)
 	       (const_int 0)))
    (set (match_dup 0)
 	(xor:SI (match_dup 0)
@@ -837,7 +837,7 @@
 	  (eq:VEC_F (match_dup 1)
 		    (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(lt:SI (reg:CC CR6_REGNO)
+	(eq:SI (reg:CC CR6_REGNO)
 	       (const_int 0)))
    (set (match_dup 0)
 	(xor:SI (match_dup 0)