[PATCH] Switch vec_init and vec_extract optabs to 2 mode optab to allow extraction of vector from vector or initialization of vector from smaller vectors (PR target/80846)

[Segher Boessenkool]

On Wed, Jul 26, 2017 at 09:09:04AM +0200, Jakub Jelinek wrote:
> On Tue, Jul 25, 2017 at 03:52:56PM -0500, Segher Boessenkool wrote:
> > On Tue, Jul 25, 2017 at 11:14:32AM +0200, Jakub Jelinek wrote:
> > > This patch only adds new vector from vector extract and init patterns to
> > > the i386 backend, but I had to change many other targets too, because
> > > it needs to have the element mode in the vec_extract/vec_init expander
> > > names.  Seems most of the backends didn't really have a mode attribute
> > > usable for this or had it only in uppercase, while for the names we need
> > > lowercase.  Some backends had a convention on how to name lower case
> > > vs. upper case modes, others didn't have any.  So I'm CCing maintainers
> > > of affected backends to seek advice on what mode attributes they want to
> > > use.
> > 
> > Would it be possible (and useful) to _also_ keep the old names?  Or do
> > you expect all targets will want to support all combinations?
> 
> Richi's preference was to use only a single conversion optab instead of
> old + new when we've discussed it on IRC.  Of course it would be far less
> work for me to support say:
> OPTAB_CD(vec_extract2_optab, "vec_extract$a$b")
> OPTAB_CD(vec_init2_optab, "vec_init$a$b")
> OPTAB_D (vec_extract_optab, "vec_extract$a")
> OPTAB_D (vec_init_optab, "vec_init$a")
> where the single mode vec_extract/vec_init would be
> extraction/initialization from element mode and the two mode one would be
> used for 2 vector modes.  If there is agreement on that, most of the
> config/*/* changes could go away.

And less work for backends, old as well as new.

> > > @@ -520,6 +520,17 @@ (define_mode_attr VEL [(V8QI "QI") (V16Q
> > >  			(SI   "SI") (HI   "HI")
> > >  			(QI   "QI")])
> > >  
> > > +;; Define element mode for each vector mode (lower case).
> > > +(define_mode_attr Vel [(V8QI "qi") (V16QI "qi")
> > > +			(V4HI "hi") (V8HI "hi")
> > > +			(V2SI "si") (V4SI "si")
> > > +			(DI "di")   (V2DI "di")
> > > +			(V4HF "hf") (V8HF "hf")
> > > +			(V2SF "sf") (V4SF "sf")
> > > +			(V2DF "df") (DF "df")
> > > +			(SI   "si") (HI   "hi")
> > > +			(QI   "qi")])
> > 
> > (Inconsistent spacing, please fix).
> 
> It is the same spacing as in VEL right above it, I've tried to follow
> whatever weirdo formatting each backend had.
> 
> > ("vel" instead of "Vel" for this name?)
> 
> That is to follow aarch64 iterator naming convention, where they have

Ugh, for some reason I thought this was in rs6000/ as well.  I have
fresh coffee now.  Sorry.


Segher