[PATCH][MIPS] MSA machine description fixes

[Moore, Catherine]

> The patch fixes some bugs as mentioned below.
> 
> 1. mips_gen_const_int_vector(): Change type for argument VAL from
> int to HOST_WIDE_INT to allow const vector of type doubleword. It in
> turn enables generation of BCLRI.d instead of AND.d for immediate
> const vector operand with only one bit clear.
> 
> 2. MSA dot product family instruction for .d format: Fix wrong MODE
> for vec_select in the second mult operand. It enables some
> optimizations like CSE fwprop etc.
> 
> 3. signed min/max immediate: Fix print operand code so as to print
> signed immediate instead of an unsigned one.
> 
> 4. MSA max/min absolute instruction family: Introduce mode iterator
> in if_then_else construct. It enables some optimizations like CSE
> fwprop etc.
> 
> Tests for all of them are also included in the patch.
> 
> Ok for trunk?
> 
> Changelog:
> 
> 2017-02-07  Prachi Godbole  <prachi.godbole@imgtec.com>
> 
> gcc/
> 	* config/mips/mips-msa.md (msa_dotp_<su>_d,
> msa_dpadd_<su>_d,
> 	msa_dpsub_<su>_d): Fix MODE for vec_select.
> 	(msa_fmax_a_<msafmt>, msa_fmin_a_<msafmt>,
> msa_max_a_<msafmt>,
> 	msa_min_a_<msafmt>): Introduce mode interator for
> if_then_else.
> 	(smin<mode>3, smax<mode>3): Change operand print code
> from 'B' to 'E'.
> 	* config/mips/mips.c (mips_gen_const_int_vector): Change
> type of last
> 	argument.
> 	* config/mips/mips-protos.h (mips_gen_const_int_vector):
> Likewise.
> 
Hi Prachi,

This part of the patch is fine, although I would like you to split it into three patches giving a separate commit for each bug fix.

> gcc/testsuite/
> 	* gcc.target/mips/msa-1.c: New tests.

The testsuite patch should be split be split as well.  I have a couple of comments on the test itself.
> 
> 
> Index: gcc/testsuite/gcc.target/mips/msa-1.c
> ==========================================================
> =========
> --- gcc/testsuite/gcc.target/mips/msa-1.c       (revision 0)
> +++ gcc/testsuite/gcc.target/mips/msa-1.c       (revision 0)
> @@ -0,0 +1,69 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa" } */
> +
> +typedef int v4i32 __attribute__ ((vector_size(16)));
> +typedef long long v2i64 __attribute__ ((vector_size(16)));
> +typedef float v4f32 __attribute__ ((vector_size(16)));
> +
> +/* Test MSA AND.d optimization: generate BCLRI.d instead, for
> immediate const
> +   vector operand with only one bit clear.  */
> +
> +void
> +and_d_msa (v2i64 *vx, v2i64 *vy)
> +{
> +  v2i64 and_vec = {0x7FFFFFFFFFFFFFFF, 0x7FFFFFFFFFFFFFFF};
> +  *vy = (*vx) & and_vec;
> +}

I know that compiler crashed for this test, but let's test for the generation of the BCLRI as well.

> +
> +/* Test MSA dot product family for CSE optimization.  */
> +
> +static v4i32 g = {0, 92, 93, 94};
> +static v4i32 h = {12, 24, 36, 48};
> +static v2i64 l = {84, 98};
> +
> +void
> +dotp_d_msa (v2i64 *c)
> +{
> +  l = __builtin_msa_dotp_s_d (g, h);
> +}
> +
> +void
> +dpadd_d_msa (v2i64 *c)
> +{
> +  *c = __builtin_msa_dpadd_s_d (l, g, h);
> +}
> +
> +void
> +dpsub_d_msa (v2i64 *c)
> +{
> +  *c = __builtin_msa_dpsub_s_d (l, g, h);
> +}

Likewise.  Can you test the assembly or one of the dumps for the optimization that you're looking for?

> +
> +/* Test MSA signed min/max immediate for correct assembly output.
> */
> +
> +void
> +min_s_msa (v4i32 *vx, v4i32 *vy)
> +{
> +  *vy = __builtin_msa_mini_s_w (*vx, -15);
> +}
> +/* { dg-final { scan-assembler "-15" } }  */
> +
> +void
> +max_s_msa (v4i32 *vx, v4i32 *vy)
> +{
> +  *vy = __builtin_msa_maxi_s_w (*vx, -15);
> +}
> +/* { dg-final { scan-assembler "-15" } }  */
> +
> +/* Test MSA min_a/max_a instructions for forward propagation
> optimization.  */
> +
> +#define FUNC(NAME, TYPE, RETTYPE) RETTYPE NAME##_a_msa (TYPE
> *vx, TYPE *vy) \
> +{ \
> +  TYPE dest = __builtin_msa_##NAME##_a_w (*vx, *vy); \
> +  return dest[0]; \
> +}
> +
> +FUNC(fmin, v4f32, float)
> +FUNC(fmax, v4f32, float)
> +FUNC(min, v4i32, int)
> +FUNC(max, v4i32, int)

This is OK.

Please repost the patches with the modifications.
Thanks,
Catherine