[PATCH] Don't error about x86 return value in SSE reg (or x86 reg) or argument in SSE reg too early (PR target/80298)

[Uros Bizjak]

On Tue, Apr 4, 2017 at 9:24 PM, Jakub Jelinek <jakub@redhat.com> wrote:
> Hi!
>
> aggregate_value_p is called often very early during compilation, e.g.
> from allocate_function or during gimplification of a call with lhs.
> The problem with that is e.g. that on x86_64 -m64 -mno-sse we can't
> include <x86intrin.h>, because the always_inline inline functions
> in mmx and 3dnow intrinsic headers return __m64 or take __m64 as arguments
> and that in the 64-bit ABI is in SSE register.
>
> The following patch makes sure we diagnose this only later (e.g. when
> expanding a function to RTL or when expanding calls to other functions),
> which means we don't diagnose e.g. inline functions that got successfully
> inlined (because then there is really no function return in SSE or x87
> reg) or e.g. for builtin calls if they are emitted inline rather than
> as a library call (again, I think that is desirable).
> I had to tweak a few tests because the reported line changed slightly,
> and in the last test add -fno-builtin-fminl, because otherwise fminl
> is expanded inline and again there is no call left with the problem.
>
> Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?

No, I think the issue should be fixed in intrinsics.

Attached patch solves this problem for me, and also fixes a couple of
similar problems (one with -m3dnowa, that is nowadays a regular
compile option). The patched intrinsics were tested with combinations
of -m{,no-}sse{,2}, -m{,no-}mmx, -m{-no}3dnow{,a}, -m64, and there
were no problems with any combination.

Uros.
-------------- next part --------------
diff --git a/gcc/config/i386/mm3dnow.h b/gcc/config/i386/mm3dnow.h
index c8a91a1..2d5c538 100644
--- a/gcc/config/i386/mm3dnow.h
+++ b/gcc/config/i386/mm3dnow.h
@@ -30,9 +30,13 @@
 #include <mmintrin.h>
 #include <prfchwintrin.h>
 
-#ifndef __3dNOW__
+#if defined __x86_64__ && !defined __SSE__ || !defined __3dNOW__
 #pragma GCC push_options
+#ifdef __x86_64__
+#pragma GCC target("sse,3dnow")
+#else
 #pragma GCC target("3dnow")
+#endif
 #define __DISABLE_3dNOW__
 #endif /* __3dNOW__ */
 
@@ -176,7 +180,20 @@ _m_to_float (__m64 __A)
   return __tmp.a[0];
 }
 
-#ifdef __3dNOW_A__
+#ifdef __DISABLE_3dNOW__
+#undef __DISABLE_3dNOW__
+#pragma GCC pop_options
+#endif /* __DISABLE_3dNOW__ */
+
+#if defined __x86_64__ && !defined __SSE__ || !defined __3dNOW_A__
+#pragma GCC push_options
+#ifdef __x86_64__
+#pragma GCC target("sse,3dnowa")
+#else
+#pragma GCC target("3dnowa")
+#endif
+#define __DISABLE_3dNOW_A__
+#endif /* __3dNOW_A__ */
 
 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 _m_pf2iw (__m64 __A)
@@ -208,11 +225,9 @@ _m_pswapd (__m64 __A)
   return (__m64)__builtin_ia32_pswapdsf ((__v2sf)__A);
 }
 
-#endif /* __3dNOW_A__ */
-
-#ifdef __DISABLE_3dNOW__
-#undef __DISABLE_3dNOW__
+#ifdef __DISABLE_3dNOW_A__
+#undef __DISABLE_3dNOW_A__
 #pragma GCC pop_options
-#endif /* __DISABLE_3dNOW__ */
+#endif /* __DISABLE_3dNOW_A__ */
 
 #endif /* _MM3DNOW_H_INCLUDED */
diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h
index 957d766..2cb73e3 100644
--- a/gcc/config/i386/mmintrin.h
+++ b/gcc/config/i386/mmintrin.h
@@ -27,9 +27,13 @@
 #ifndef _MMINTRIN_H_INCLUDED
 #define _MMINTRIN_H_INCLUDED
 
-#ifndef __MMX__
+#if defined __x86_64__ && !defined __SSE__ || !defined __MMX__
 #pragma GCC push_options
+#ifdef __x86_64__
+#pragma GCC target("sse,mmx")
+#else
 #pragma GCC target("mmx")
+#endif
 #define __DISABLE_MMX__
 #endif /* __MMX__ */
 
@@ -311,7 +315,7 @@ _m_paddd (__m64 __m1, __m64 __m2)
 /* Add the 64-bit values in M1 to the 64-bit values in M2.  */
 #ifndef __SSE2__
 #pragma GCC push_options
-#pragma GCC target("sse2")
+#pragma GCC target("sse2,mmx")
 #define __DISABLE_SSE2__
 #endif /* __SSE2__ */
 
@@ -423,7 +427,7 @@ _m_psubd (__m64 __m1, __m64 __m2)
 /* Add the 64-bit values in M1 to the 64-bit values in M2.  */
 #ifndef __SSE2__
 #pragma GCC push_options
-#pragma GCC target("sse2")
+#pragma GCC target("sse2,mmx")
 #define __DISABLE_SSE2__
 #endif /* __SSE2__ */