[PATCH][AArch64] Add a SHA1H pattern

James Greenhalgh james.greenhalgh@arm.com
Fri Oct 28 15:58:00 GMT 2016


On Fri, Oct 28, 2016 at 04:54:05PM +0100, Wilco Dijkstra wrote:
> James Greenhalgh wrote:
> > On Wed, Oct 26, 2016 at 12:11:44PM +0000, Wilco Dijkstra wrote:
> > > Add a SHA1H pattern with a V2SI input.  This avoids unnecessary
> > > DUPs when using intrinsics like vsha1h_u32 (vgetq_lane_u32 (x, 0)).
> >
> > I think this is incorrect for big endian - element 0 of a vec_select in
> > big-endian for V4SImode is the high 32-bits (i.e. bits 96-127 of the
> > architected register). I think you'd need two patterns, one as below for
> > !BYTES_BIG_ENDIAN, and one selecting element 3 for BYTES_BIG_ENDIAN.
> 
> Yes that's true, big-endian SIMD works in mysterious ways... Here is the updated
> patch (tested on aarch64_be-none-elf too):
> 
> Add LE/BE SHA1H patterns with a V2SI input.  This avoids unnecessary
> DUPs when using intrinsics like vsha1h_u32 (vgetq_lane_u32 (x, 0)).


Thanks, this respin looks OK to me.

James

> ChangeLog:
> 2016-10-28  Wilco Dijkstra  <wdijkstr@arm.com>
> 
> 	* config/aarch64/aarch64-simd.md (aarch64_crypto_sha1hv4si): New pattern.
> 	(aarch64_be_crypto_sha1hv4si): New pattern.
> --



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