[PATCH, ARM 5/7, ping3] Adapt other atomic operations to ARMv8-M Baseline
Thomas Preudhomme
thomas.preudhomme@foss.arm.com
Thu Oct 27 10:21:00 GMT 2016
On 27/10/16 09:50, Kyrill Tkachov wrote:
> Hi Thomas,
>
> On 24/10/16 09:05, Thomas Preudhomme wrote:
>> Ping?
>>
>> Best regards,
>>
>> Thomas
>>
>> On 14/10/16 14:51, Thomas Preudhomme wrote:
>>> Ping?
>>>
>>> Best regards,
>>>
>>> Thomas
>>>
>>> On 03/10/16 17:45, Thomas Preudhomme wrote:
>>>> Ping?
>>>>
>>>> Best regards,
>>>>
>>>> Thomas
>>>>
>>>> On 22/09/16 14:47, Thomas Preudhomme wrote:
>>>>> Hi,
>>>>>
>>>>> This patch is part of a patch series to add support for atomic operations on
>>>>> ARMv8-M Baseline targets in GCC. This specific patch adds support for
>>>>> remaining
>>>>> atomic operations (exchange, addition, substraction, bitwise AND, OR, XOR and
>>>>> NAND to ARMv8-M Baseline, doubleword integers excepted. As with the previous
>>>>> patch in the patch series, this mostly consists adding Thumb-1 specific
>>>>> constraints to atomic_* patterns to match those in thumb1.md for the non
>>>>> atomic
>>>>> operation.
>>>>>
>>>>> ChangeLog entry is as follows:
>>>>>
>>>>> *** gcc/ChangeLog ***
>>>>>
>>>>> 2016-09-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
>>>>>
>>>>> * config/arm/arm.c (arm_split_atomic_op): Add function comment. Add
>>>>> logic to to decide whether to copy over old value to register for new
>>>>> value.
>>>>> * config/arm/sync.md: Add comments explaning why mode and code
>>>>> attribute are not defined in iterators.md
>>>>> (thumb1_atomic_op_str): New code attribute.
>>>>> (thumb1_atomic_newop_str): Likewise.
>>>>> (thumb1_atomic_fetch_op_str): Likewise.
>>>>> (thumb1_atomic_fetch_newop_str): Likewise.
>>>>> (thumb1_atomic_fetch_oldop_str): Likewise.
>>>>> (atomic_exchange<mode>): Add new ARMv8-M Baseline only alternatives to
>>>>> mirror the more restrictive constraints of the Thumb-1 insns after
>>>>> split compared to Thumb-2 counterpart insns.
>>>>> (atomic_<sync_optab><mode>): Likewise. Add comment to keep constraints
>>>>> in sync with non atomic version.
>>>>> (atomic_nand<mode>): Likewise.
>>>>> (atomic_fetch_<sync_optab><mode>): Likewise.
>>>>> (atomic_fetch_nand<mode>): Likewise.
>>>>> (atomic_<sync_optab>_fetch<mode>): Likewise.
>>>>> (atomic_nand_fetch<mode>): Likewise.
>>>>> * config/arm/thumb1.md (thumb1_addsi3): Add comment to keep contraint
>>>>> in sync with atomic version.
>>>>> (thumb1_subsi3_insn): Likewise.
>>>>> (thumb1_andsi3_insn): Likewise.
>>>>> (thumb1_iorsi3_insn): Likewise.
>>>>> (thumb1_xorsi3_insn): Likewise.
>>>>>
>>>>>
>>>>> Testing: No code generation difference for ARMv7-A, ARMv7VE and ARMv8-A on all
>>>>> atomic and synchronization testcases in the testsuite [2]. Patchset was also
>>>>> bootstrapped with --enable-itm --enable-gomp on ARMv8-A in ARM and Thumb
>>>>> mode at
>>>>> optimization level -O1 and above [1] without any regression in the
>>>>> testsuite and
>>>>> no code generation difference in libitm and libgomp.
>>>>>
>>>>> Code generation for ARMv8-M Baseline has been manually examined and compared
>>>>> against ARMv8-A Thumb-2 for the following configuration without finding any
>>>>> issue:
>>>>>
>>>>> gcc.dg/atomic-op-2.c at -Os
>>>>> gcc.dg/atomic-compare-exchange-2.c at -Os
>>>>> gcc.dg/atomic-compare-exchange-3.c at -O3
>>>>>
>>>>>
>>>>> Is this ok for trunk?
>>>>>
>>>>> Best regards,
>>>>>
>>>>> Thomas
>>>>>
>>>>> [1] CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET were set to "-O1 -g", "-O3
>>>>> -g" and
>>>>> undefined ("-O2 -g")
>>>>> [2] The exact list is:
>>>>>
>>>>> gcc/testsuite/gcc.dg/atomic-compare-exchange-1.c
>>>>> gcc/testsuite/gcc.dg/atomic-compare-exchange-2.c
>>>>> gcc/testsuite/gcc.dg/atomic-compare-exchange-3.c
>>>>> gcc/testsuite/gcc.dg/atomic-exchange-1.c
>>>>> gcc/testsuite/gcc.dg/atomic-exchange-2.c
>>>>> gcc/testsuite/gcc.dg/atomic-exchange-3.c
>>>>> gcc/testsuite/gcc.dg/atomic-fence.c
>>>>> gcc/testsuite/gcc.dg/atomic-flag.c
>>>>> gcc/testsuite/gcc.dg/atomic-generic.c
>>>>> gcc/testsuite/gcc.dg/atomic-generic-aux.c
>>>>> gcc/testsuite/gcc.dg/atomic-invalid-2.c
>>>>> gcc/testsuite/gcc.dg/atomic-load-1.c
>>>>> gcc/testsuite/gcc.dg/atomic-load-2.c
>>>>> gcc/testsuite/gcc.dg/atomic-load-3.c
>>>>> gcc/testsuite/gcc.dg/atomic-lockfree.c
>>>>> gcc/testsuite/gcc.dg/atomic-lockfree-aux.c
>>>>> gcc/testsuite/gcc.dg/atomic-noinline.c
>>>>> gcc/testsuite/gcc.dg/atomic-noinline-aux.c
>>>>> gcc/testsuite/gcc.dg/atomic-op-1.c
>>>>> gcc/testsuite/gcc.dg/atomic-op-2.c
>>>>> gcc/testsuite/gcc.dg/atomic-op-3.c
>>>>> gcc/testsuite/gcc.dg/atomic-op-6.c
>>>>> gcc/testsuite/gcc.dg/atomic-store-1.c
>>>>> gcc/testsuite/gcc.dg/atomic-store-2.c
>>>>> gcc/testsuite/gcc.dg/atomic-store-3.c
>>>>> gcc/testsuite/g++.dg/ext/atomic-1.C
>>>>> gcc/testsuite/g++.dg/ext/atomic-2.C
>>>>> gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c
>>>>> gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c
>>>>> gcc/testsuite/gcc.target/arm/atomic-op-acquire.c
>>>>> gcc/testsuite/gcc.target/arm/atomic-op-char.c
>>>>> gcc/testsuite/gcc.target/arm/atomic-op-consume.c
>>>>> gcc/testsuite/gcc.target/arm/atomic-op-int.c
>>>>> gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c
>>>>> gcc/testsuite/gcc.target/arm/atomic-op-release.c
>>>>> gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c
>>>>> gcc/testsuite/gcc.target/arm/atomic-op-short.c
>>>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_1.c
>>>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_2.c
>>>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_3.c
>>>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_4.c
>>>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_5.c
>>>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_6.c
>>>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_7.c
>>>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_8.c
>>>>> gcc/testsuite/gcc.target/arm/atomic_loaddi_9.c
>>>>> gcc/testsuite/gcc.target/arm/sync-1.c
>>>>> gcc/testsuite/gcc.target/arm/synchronize.c
>>>>> gcc/testsuite/gcc.target/arm/armv8-sync-comp-swap.c
>>>>> gcc/testsuite/gcc.target/arm/armv8-sync-op-acquire.c
>>>>> gcc/testsuite/gcc.target/arm/armv8-sync-op-full.c
>>>>> gcc/testsuite/gcc.target/arm/armv8-sync-op-release.c
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/60658.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/62259.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/64658.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/65147.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/65913.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/70766.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/49445.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/constexpr.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/copy_list.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/default.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/direct_list.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/single_value.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/cons/user_pod.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/51811.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/56011.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_assignment.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/integral_conversion.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/operators/pointer_partial_void.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/requirements/base_classes.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/requirements/compare_exchange_lowering.cc
>>>>>
>>>>>
>>>>>
>>>>> libstdc++-v3/testsuite/29_atomics/atomic/requirements/explicit_instantiation/1.cc
>>>>>
>>>>>
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/clear/1.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/1.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/56012.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/aggregate.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/cons/default.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/requirements/standard_layout.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/requirements/trivial.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/test_and_set/explicit.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_flag/test_and_set/implicit.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/60940.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/65147.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/constexpr.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/copy_list.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/default.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/direct_list.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/single_value.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/bitwise.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/decrement.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/increment.cc
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/integral_assignment.cc
>>>>>
>>>>>
>>>>>
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/operators/integral_conversion.cc
>>>>>
>>>>>
>>>>>
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/requirements/standard_layout.cc
>>>>>
>>>>>
>>>>> libstdc++-v3/testsuite/29_atomics/atomic_integral/requirements/trivial.cc
>>>>> libstdc++-v3/testsuite/29_atomics/headers/atomic/functions_std_c++0x.cc
>>>>> libstdc++-v3/testsuite/29_atomics/headers/atomic/macros.cc
>>>>> libstdc++-v3/testsuite/29_atomics/headers/atomic/types_std_c++0x.cc
>
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index
> 9e4ff0191358f9143ee487ecc0cd60eeb91950c8..fb09dcaf5b8bf322afa9c12446983e833e9d7898
> 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -28307,6 +28307,15 @@ arm_split_compare_and_swap (rtx operands[])
> emit_label (label2);
> }
>
> +/* Split an atomic operation pattern. Operation is given by MODE and is one
> + of PLUS, MINUS, IOR, XOR, SET (for an exchange operation) or NOT (for a nand
>
> s/MODE/CODE/.
>
> + operation). Operation is performed on the content at MEM and on VALUE
> + following the memory model MODEL_RTX. The content at MEM before and after
> + the operation is returned in OLD_OUT and NEW_OUT respectively while the
> + success of the operation is returned in COND. Using a scratch register or
> + an operand register for these determines what result is returned for that
> + pattern. */
> +
> void
> arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
>
>
> <snip>
>
> This is ok with that change.
Done. Attached the patch that got committed.
Thanks.
Best regards,
Thomas
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