[rs6000] Add support for signed overflow arithmetic

[Segher Boessenkool]

On Mon, Oct 24, 2016 at 11:03:25PM +0200, Eric Botcazou wrote:
> > Let's see.  Completely untested.  Inputs in regs 3 and 4, output in reg 3.
> > 32-bit code all the way.
> > 
> > add:
> > 	eqv 9,3,4
> > 	add 3,3,4
> > 	xor 4,3,4
> > 	and. 4,9,4
> > 	blt <overflow>
> > 
> > sub:
> > 	xor 9,3,4
> > 	sub 3,3,4
> > 	eqv 4,3,4
> > 	and. 4,9,4
> > 	blt <overflow>
> 
> These ones (if correct) are quite better than the generic code!

It is nicely generic as well, but requires more insns than this if your
ISA does not have a full complement of logical ops.  Well, just an
"andnot" is enough, you don't actually need eqv here.

Addition has a signed overflow if and only if the two inputs have the
same sign, and the result has the opposite sign.  Subtraction overflows
if and only if the two inputs have opposite sign, and the subtrahend has
the same sign as the result.  Here 0 is counted as positive.

> > neg:
> > 	neg 3,3
> > 	xoris. 9,3,0x8000
> > 	beq <overflow>
> > 
> > mul:
> > 	mulhw 9,3,4
> > 	mullw 3,3,4
> > 	srawi 4,9,31
> > 	cmpw 4,9
> > 	bne <overflow>
> 
> These ones are essentially equivalent to the generic code.

And the generic one for div is as good as it gets as well I suppose?
We cannot use the result of the divide insn if it overflows (the result
is undefined), so there isn't much at all we can do.


Segher