[PATCH,rs6000] Add built-in function support for Power9 string operations

Segher Boessenkool segher@kernel.crashing.org
Tue Oct 11 17:02:00 GMT 2016


On Mon, Oct 10, 2016 at 12:11:40PM -0600, Kelvin Nilsen wrote:
> 
> This patch adds support for 26 new instructions that are introduced
> with the Power ISA 3.0 (Power9).  The instructions are lxvl, stxvl,
> vcmpneb, "vcmpneb.", vcmnezb, "vcmpnezb.", vcmpneh, "vcmpneh.", vcmpnezh,
> "vcmpnezh.", cmpnew, "vcmpnew.", vcmpnezw, "vcmpnezw.", vclzlsbb, vctzlsbb,
> vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx, vextuwrx,
> xvcmpnesp, "xvcmpnesp.", xvcmpnedp, and "xvcmpnedp.".
> 
> The new support consists in part of changes to the implementation of
> the vec_cmp_ne, vec_all_ne, and vec_any_eq functions, so that these
> built-in functions now translate into Power9 instructions when the
> target architecture supports Power9.
> 
> Additionally, the following built-in functions have been added:
> 
>    vec_all_nez: Test for all vector elements not equal and not zero
>    vec_any_eqz: Test for any vector elements equal or zero
>    vec_cmpnez: Do pairwise comparison of two vectors, setting the
>       corresponding element of the result vector to all ones if the
>       pairwise comparison finds the pair of incoming values are not
>       equal of if either of the pair's values equals zero.
>    vec_cntlz_lsbb: Count leading zeros of least significant byte bits.
>    vec_cnttz_lsbb: Count trailing zeros of least significant byte bits.
>    vec_xl_len: Load a variable length vector from memory.
>    vec_xst_len: Store a variable lenght vector to memory.
>    vec_xlx: Extract element from vector left indexed.
>    vec_xrx: Extract element from vector right indexed.
> 
> All of the built-in functions mentioned above conform to a draft
> update of "Power Architecture 64-Bit ELF V2 ABI Specification",
> also known as "OpenPOWER ABI for Linux Supplement".
> 
> New tests have been added to exercise each of the new functions
> and to exercise the non-deprecated forms of the modified functions.
> 
> This patch has been bootstrapped and tested on
> powerpc64le-unknown-linux (little-endian) and on
> powerpc64-unknown-linux (big-endian, with both -m32 and -m64 target
> options) with no regressions.  Is this ok for the trunk? 

> 	(vec_any_eq): Revised macro under _ARCH_PWR9 conditional
> 	compilation. 

Trailing space.  There are a few more; please fix all.

>  static rtx
> +altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
> +{
> +  rtx pat;
> +  tree arg0 = CALL_EXPR_ARG (exp, 0);
> +  tree arg1 = CALL_EXPR_ARG (exp, 1);
> +  tree arg2 = CALL_EXPR_ARG (exp, 2);
> +  rtx op0 = expand_normal (arg0);
> +  rtx op1 = expand_normal (arg1);
> +  rtx op2 = expand_normal (arg2);
> +  /*  machine_mode tmode = insn_data[icode].operand[0].mode; */

Delete that last line?  Or is it useful some way?

> +;; ISA 3.0 String Operations (VSU) Support

What does "VSU" here mean?  (Don't tell me, put it in the patch :-) )

> +(define_insn "*vsx_ne_<mode>_p"
> +  [(set (reg:CC 74)

Please don't hardcode the register number.  CR6_REGNO instead.  I thought
I changed it everywhere?  Is your base an old tree?

> +(define_insn "*stxvl"
> +  [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
> +	(unspec:V16QI
> +	 [(match_operand:V16QI 0 "vsx_register_operand" "wa")
> +	  (match_operand:DI 2 "register_operand" "r")]
> +	 UNSPEC_STXVL))]
> +  "TARGET_P9_VECTOR && TARGET_64BIT"
> +  "sldi %2,%2\;stxvl %x0,%1,%2"

On all these patterns you change operand 2, but the constraints don't
say; that probably will not work correctly?  I'm thinking you need "+r".

> -;; Vec int modes
> -(define_mode_iterator VI [V4SI V8HI V16QI])
>  ;; Like VI, but add ISA 2.07 integer vector ops
>  (define_mode_iterator VI2 [V4SI V8HI V16QI V2DI])

"Like VI", but you removed VI.

> Index: gcc/config/rs6000/vector.md
> ===================================================================
> --- gcc/config/rs6000/vector.md	(revision 239612)
> +++ gcc/config/rs6000/vector.md	(working copy)
> @@ -61,6 +61,9 @@
>  ;; Vector modes for 64-bit base types
>  (define_mode_iterator VEC_64 [V2DI V2DF])
>  
> +;; Vector integer modes
> +(define_mode_iterator VI [V4SI V8HI V16QI])

... oh, you added it back here?  Why?

> +;; This expansion handles the V16QI, V8HI, and V4SI modes in the
> +;; implementation of the vec_all_ne and vec_any_eq built-in functions
> +;; on Power9.
> +(define_expand "vector_ne_<mode>_p"
> +  [(parallel
> +    [(set (reg:CC 74)
> +	  (unspec:CC [(ne:CC (match_operand:VI 1 "vlogical_operand" "")
> +			     (match_operand:VI 2 "vlogical_operand" ""))]
> +	   UNSPEC_PREDICATE))
> +     (set (match_operand:VI 0 "vlogical_operand" "")
> +	  (ne:VI (match_dup 1)
> +		 (match_dup 2)))])]
> +  "TARGET_P9_VECTOR"
> +  "")

You can drop the default args (the "" at the end of operands).

> +/* Overloaded CMPNE support was implemented prior to Power 9,
> +   so is not mentioned here.  */
> +BU_P9V_OVERLOAD_2 (CMPNEZ,	"vcmpnez")
> +
> +BU_P9V_OVERLOAD_P (VCMPNEZ_P,   "vcmpnez_p")
> +BU_P9V_OVERLOAD_P (VCMPNE_P,   "vcmpne_p")

Tabs instead of spaces here, too?


Please fix these and repost.  Thanks,


Segher



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