[PATCH] Remove constraints from further i386 define_expand patterns
Jakub Jelinek
jakub@redhat.com
Mon May 9 16:49:00 GMT 2016
Hi!
I believe this cleans up all remaining define_expands (have looked
at tmp-mddump.md with sed picking up only define_expand patterns in there
and have been looking for any constraints and none were left).
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2016-05-09 Jakub Jelinek <jakub@redhat.com>
* config/i386/i386.md (reload_noff_store, reload_noff_load, set_got,
set_got_labelled, lwp_llwpcb, lwp_lwpval<mode>3, lwp_lwpins<mode>3):
Remove constraints from expanders.
* config/i386/sse.md (vec_interleave_high<mode>,
vec_interleave_low<mode>, <avx512>_vpermi2var<mode>3_maskz,
<avx512>_vpermt2var<mode>3_maskz): Likewise.
--- gcc/config/i386/i386.md.jj 2016-05-09 11:38:36.000000000 +0200
+++ gcc/config/i386/i386.md 2016-05-09 13:33:12.883238591 +0200
@@ -1891,9 +1891,9 @@ (define_insn "*popfl<mode>1"
;; Reload patterns to support multi-word load/store
;; with non-offsetable address.
(define_expand "reload_noff_store"
- [(parallel [(match_operand 0 "memory_operand" "=m")
- (match_operand 1 "register_operand" "r")
- (match_operand:DI 2 "register_operand" "=&r")])]
+ [(parallel [(match_operand 0 "memory_operand")
+ (match_operand 1 "register_operand")
+ (match_operand:DI 2 "register_operand")])]
"TARGET_64BIT"
{
rtx mem = operands[0];
@@ -1907,9 +1907,9 @@ (define_expand "reload_noff_store"
})
(define_expand "reload_noff_load"
- [(parallel [(match_operand 0 "register_operand" "=r")
- (match_operand 1 "memory_operand" "m")
- (match_operand:DI 2 "register_operand" "=r")])]
+ [(parallel [(match_operand 0 "register_operand")
+ (match_operand 1 "memory_operand")
+ (match_operand:DI 2 "register_operand")])]
"TARGET_64BIT"
{
rtx mem = operands[1];
@@ -12522,7 +12522,7 @@ (define_expand "prologue"
(define_expand "set_got"
[(parallel
- [(set (match_operand:SI 0 "register_operand" "=r")
+ [(set (match_operand:SI 0 "register_operand")
(unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
(clobber (reg:CC FLAGS_REG))])]
"!TARGET_64BIT"
@@ -12542,7 +12542,7 @@ (define_insn "*set_got"
(define_expand "set_got_labelled"
[(parallel
- [(set (match_operand:SI 0 "register_operand" "=r")
+ [(set (match_operand:SI 0 "register_operand")
(unspec:SI [(label_ref (match_operand 1))]
UNSPEC_SET_GOT))
(clobber (reg:CC FLAGS_REG))])]
@@ -19041,7 +19041,7 @@ (define_insn "fnclex"
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_expand "lwp_llwpcb"
- [(unspec_volatile [(match_operand 0 "register_operand" "r")]
+ [(unspec_volatile [(match_operand 0 "register_operand")]
UNSPECV_LLWP_INTRINSIC)]
"TARGET_LWP")
@@ -19055,7 +19055,7 @@ (define_insn "*lwp_llwpcb<mode>1"
(set_attr "length" "5")])
(define_expand "lwp_slwpcb"
- [(set (match_operand 0 "register_operand" "=r")
+ [(set (match_operand 0 "register_operand")
(unspec_volatile [(const_int 0)] UNSPECV_SLWP_INTRINSIC))]
"TARGET_LWP"
{
@@ -19079,9 +19079,9 @@ (define_insn "lwp_slwpcb<mode>"
(set_attr "length" "5")])
(define_expand "lwp_lwpval<mode>3"
- [(unspec_volatile [(match_operand:SWI48 1 "register_operand" "r")
- (match_operand:SI 2 "nonimmediate_operand" "rm")
- (match_operand:SI 3 "const_int_operand" "i")]
+ [(unspec_volatile [(match_operand:SWI48 1 "register_operand")
+ (match_operand:SI 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_int_operand")]
UNSPECV_LWPVAL_INTRINSIC)]
"TARGET_LWP"
;; Avoid unused variable warning.
@@ -19101,11 +19101,11 @@ (define_insn "*lwp_lwpval<mode>3_1"
(define_expand "lwp_lwpins<mode>3"
[(set (reg:CCC FLAGS_REG)
- (unspec_volatile:CCC [(match_operand:SWI48 1 "register_operand" "r")
- (match_operand:SI 2 "nonimmediate_operand" "rm")
- (match_operand:SI 3 "const_int_operand" "i")]
+ (unspec_volatile:CCC [(match_operand:SWI48 1 "register_operand")
+ (match_operand:SI 2 "nonimmediate_operand")
+ (match_operand:SI 3 "const_int_operand")]
UNSPECV_LWPINS_INTRINSIC))
- (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
+ (set (match_operand:QI 0 "nonimmediate_operand")
(eq:QI (reg:CCC FLAGS_REG) (const_int 0)))]
"TARGET_LWP")
--- gcc/config/i386/sse.md.jj 2016-05-09 13:15:55.000000000 +0200
+++ gcc/config/i386/sse.md 2016-05-09 13:31:21.086735811 +0200
@@ -11991,9 +11991,9 @@ (define_insn "vec_interleave_lowv4si<mas
(set_attr "mode" "TI")])
(define_expand "vec_interleave_high<mode>"
- [(match_operand:VI_256 0 "register_operand" "=x")
- (match_operand:VI_256 1 "register_operand" "x")
- (match_operand:VI_256 2 "nonimmediate_operand" "xm")]
+ [(match_operand:VI_256 0 "register_operand")
+ (match_operand:VI_256 1 "register_operand")
+ (match_operand:VI_256 2 "nonimmediate_operand")]
"TARGET_AVX2"
{
rtx t1 = gen_reg_rtx (<MODE>mode);
@@ -12009,9 +12009,9 @@ (define_expand "vec_interleave_high<mode
})
(define_expand "vec_interleave_low<mode>"
- [(match_operand:VI_256 0 "register_operand" "=x")
- (match_operand:VI_256 1 "register_operand" "x")
- (match_operand:VI_256 2 "nonimmediate_operand" "xm")]
+ [(match_operand:VI_256 0 "register_operand")
+ (match_operand:VI_256 1 "register_operand")
+ (match_operand:VI_256 2 "nonimmediate_operand")]
"TARGET_AVX2"
{
rtx t1 = gen_reg_rtx (<MODE>mode);
@@ -17337,11 +17337,11 @@ (define_insn "<sse2_avx_avx512f>_vpermil
(set_attr "mode" "<sseinsnmode>")])
(define_expand "<avx512>_vpermi2var<mode>3_maskz"
- [(match_operand:VI48F 0 "register_operand" "=v")
- (match_operand:VI48F 1 "register_operand" "v")
- (match_operand:<sseintvecmode> 2 "register_operand" "0")
- (match_operand:VI48F 3 "nonimmediate_operand" "vm")
- (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")]
+ [(match_operand:VI48F 0 "register_operand")
+ (match_operand:VI48F 1 "register_operand")
+ (match_operand:<sseintvecmode> 2 "register_operand")
+ (match_operand:VI48F 3 "nonimmediate_operand")
+ (match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512F"
{
emit_insn (gen_<avx512>_vpermi2var<mode>3_maskz_1 (
@@ -17365,11 +17365,11 @@ (define_expand "<avx512>_vpermi2var<mode
})
(define_expand "<avx512>_vpermi2var<mode>3_maskz"
- [(match_operand:VI2_AVX512VL 0 "register_operand" "=v")
- (match_operand:VI2_AVX512VL 1 "register_operand" "v")
- (match_operand:<sseintvecmode> 2 "register_operand" "0")
- (match_operand:VI2_AVX512VL 3 "nonimmediate_operand" "vm")
- (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")]
+ [(match_operand:VI2_AVX512VL 0 "register_operand")
+ (match_operand:VI2_AVX512VL 1 "register_operand")
+ (match_operand:<sseintvecmode> 2 "register_operand")
+ (match_operand:VI2_AVX512VL 3 "nonimmediate_operand")
+ (match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512BW"
{
emit_insn (gen_<avx512>_vpermi2var<mode>3_maskz_1 (
@@ -17466,11 +17466,11 @@ (define_insn "<avx512>_vpermi2var<mode>3
(set_attr "mode" "<sseinsnmode>")])
(define_expand "<avx512>_vpermt2var<mode>3_maskz"
- [(match_operand:VI48F 0 "register_operand" "=v")
- (match_operand:<sseintvecmode> 1 "register_operand" "v")
- (match_operand:VI48F 2 "register_operand" "0")
- (match_operand:VI48F 3 "nonimmediate_operand" "vm")
- (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")]
+ [(match_operand:VI48F 0 "register_operand")
+ (match_operand:<sseintvecmode> 1 "register_operand")
+ (match_operand:VI48F 2 "register_operand")
+ (match_operand:VI48F 3 "nonimmediate_operand")
+ (match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512F"
{
emit_insn (gen_<avx512>_vpermt2var<mode>3_maskz_1 (
@@ -17480,11 +17480,11 @@ (define_expand "<avx512>_vpermt2var<mode
})
(define_expand "<avx512>_vpermt2var<mode>3_maskz"
- [(match_operand:VI1_AVX512VL 0 "register_operand" "=v")
- (match_operand:<sseintvecmode> 1 "register_operand" "v")
- (match_operand:VI1_AVX512VL 2 "register_operand" "0")
- (match_operand:VI1_AVX512VL 3 "nonimmediate_operand" "vm")
- (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")]
+ [(match_operand:VI1_AVX512VL 0 "register_operand")
+ (match_operand:<sseintvecmode> 1 "register_operand")
+ (match_operand:VI1_AVX512VL 2 "register_operand")
+ (match_operand:VI1_AVX512VL 3 "nonimmediate_operand")
+ (match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512VBMI"
{
emit_insn (gen_<avx512>_vpermt2var<mode>3_maskz_1 (
@@ -17494,11 +17494,11 @@ (define_expand "<avx512>_vpermt2var<mode
})
(define_expand "<avx512>_vpermt2var<mode>3_maskz"
- [(match_operand:VI2_AVX512VL 0 "register_operand" "=v")
- (match_operand:<sseintvecmode> 1 "register_operand" "v")
- (match_operand:VI2_AVX512VL 2 "register_operand" "0")
- (match_operand:VI2_AVX512VL 3 "nonimmediate_operand" "vm")
- (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")]
+ [(match_operand:VI2_AVX512VL 0 "register_operand")
+ (match_operand:<sseintvecmode> 1 "register_operand")
+ (match_operand:VI2_AVX512VL 2 "register_operand")
+ (match_operand:VI2_AVX512VL 3 "nonimmediate_operand")
+ (match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512BW"
{
emit_insn (gen_<avx512>_vpermt2var<mode>3_maskz_1 (
Jakub
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