[PATCH, i386]: Change true_regnum to REGNO in peephole2 and post-reload splitters
Uros Bizjak
ubizjak@gmail.com
Thu May 5 20:38:00 GMT 2016
Hello!
There is no point to determine regno of register operand using
true_regnum in peephole2s and post-reload splitters. REGNO can be used
instead.
2016-05-05 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (peehole2 patterns): Change true_regnum
to REGNO in all peephole2 patterns.
(post-reload splitters): Change true_regnum to REGNO in
post-reload splitters.
(zero_extend splitters): Use general_reg_operand and
nonimmediate_gr_operand predicates.
Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline SVN.
Uros.
-------------- next part --------------
Index: i386.md
===================================================================
--- i386.md (revision 235906)
+++ i386.md (working copy)
@@ -3777,20 +3777,18 @@
"split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
(define_split
- [(set (match_operand:DI 0 "register_operand")
- (zero_extend:DI (match_operand:SI 1 "register_operand")))]
+ [(set (match_operand:DI 0 "general_reg_operand")
+ (zero_extend:DI (match_operand:SI 1 "general_reg_operand")))]
"!TARGET_64BIT && reload_completed
- && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))
- && true_regnum (operands[0]) == true_regnum (operands[1])"
+ && REGNO (operands[0]) == REGNO (operands[1])"
[(set (match_dup 4) (const_int 0))]
"split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
(define_split
- [(set (match_operand:DI 0 "nonimmediate_operand")
- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
+ [(set (match_operand:DI 0 "nonimmediate_gr_operand")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_gr_operand")))]
"!TARGET_64BIT && reload_completed
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))
- && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))"
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
[(set (match_dup 3) (match_dup 1))
(set (match_dup 4) (const_int 0))]
"split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
@@ -3828,7 +3826,8 @@
[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
{
- if (true_regnum (operands[0]) != true_regnum (operands[1]))
+ if (!REG_P (operands[1])
+ || REGNO (operands[0]) != REGNO (operands[1]))
{
ix86_expand_clear (operands[0]);
@@ -3875,7 +3874,8 @@
[(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
(clobber (reg:CC FLAGS_REG))])]
{
- if (true_regnum (operands[0]) != true_regnum (operands[1]))
+ if (!REG_P (operands[1])
+ || REGNO (operands[0]) != REGNO (operands[1]))
{
ix86_expand_clear (operands[0]);
@@ -3988,8 +3988,8 @@
/* Generate a cltd if possible and doing so it profitable. */
if ((optimize_function_for_size_p (cfun) || TARGET_USE_CLTD)
- && true_regnum (operands[1]) == AX_REG
- && true_regnum (operands[2]) == DX_REG)
+ && REGNO (operands[1]) == AX_REG
+ && REGNO (operands[2]) == DX_REG)
{
emit_insn (gen_ashrsi3_cvt (operands[2], operands[1], GEN_INT (31)));
}
@@ -4030,8 +4030,8 @@
(set (match_operand:SI 3 "memory_operand") (match_dup 2))]
"/* cltd is shorter than sarl $31, %eax */
!optimize_function_for_size_p (cfun)
- && true_regnum (operands[1]) == AX_REG
- && true_regnum (operands[2]) == DX_REG
+ && REGNO (operands[1]) == AX_REG
+ && REGNO (operands[2]) == DX_REG
&& peep2_reg_dead_p (2, operands[1])
&& peep2_reg_dead_p (3, operands[2])
&& !reg_mentioned_p (operands[2], operands[3])"
@@ -4052,19 +4052,19 @@
{
split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);
- if (true_regnum (operands[3]) != true_regnum (operands[1]))
+ if (REGNO (operands[3]) != REGNO (operands[1]))
emit_move_insn (operands[3], operands[1]);
/* Generate a cltd if possible and doing so it profitable. */
if ((optimize_function_for_size_p (cfun) || TARGET_USE_CLTD)
- && true_regnum (operands[3]) == AX_REG
- && true_regnum (operands[4]) == DX_REG)
+ && REGNO (operands[3]) == AX_REG
+ && REGNO (operands[4]) == DX_REG)
{
emit_insn (gen_ashrsi3_cvt (operands[4], operands[3], GEN_INT (31)));
DONE;
}
- if (true_regnum (operands[4]) != true_regnum (operands[1]))
+ if (REGNO (operands[4]) != REGNO (operands[1]))
emit_move_insn (operands[4], operands[1]);
emit_insn (gen_ashrsi3_cvt (operands[4], operands[4], GEN_INT (31)));
@@ -5207,7 +5207,7 @@
"TARGET_SSE_PARTIAL_REG_DEPENDENCY
&& optimize_function_for_speed_p (cfun)
&& epilogue_completed
- && (!SSE_REG_P (operands[1])
+ && (!REG_P (operands[1])
|| REGNO (operands[0]) != REGNO (operands[1]))
&& (!EXT_REX_SSE_REG_P (operands[0])
|| TARGET_AVX512VL)"
@@ -5235,7 +5235,7 @@
"TARGET_SSE_PARTIAL_REG_DEPENDENCY
&& optimize_function_for_speed_p (cfun)
&& epilogue_completed
- && (!SSE_REG_P (operands[1])
+ && (!REG_P (operands[1])
|| REGNO (operands[0]) != REGNO (operands[1]))
&& (!EXT_REX_SSE_REG_P (operands[0])
|| TARGET_AVX512VL)"
@@ -7196,7 +7196,7 @@
(match_operand:DWIH 2 "nonimmediate_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2 && reload_completed
- && true_regnum (operands[1]) == DX_REG"
+ && REGNO (operands[1]) == DX_REG"
[(parallel [(set (match_dup 3)
(mult:DWIH (match_dup 1) (match_dup 2)))
(set (match_dup 4)
@@ -8341,7 +8341,8 @@
(match_operand:SWI248 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
- && true_regnum (operands[0]) != true_regnum (operands[1])"
+ && (!REG_P (operands[1])
+ || REGNO (operands[0]) != REGNO (operands[1]))"
[(const_int 0)]
{
HOST_WIDE_INT ival = INTVAL (operands[2]);
@@ -9302,12 +9303,12 @@
[(set (match_dup 0) (match_op_dup 1 [(match_dup 0)]))])
(define_split
- [(set (match_operand 0 "register_operand")
+ [(set (match_operand 0 "sse_reg_operand")
(match_operator 3 "absneg_operator"
[(match_operand 1 "register_operand")]))
(use (match_operand 2 "nonimmediate_operand"))
(clobber (reg:CC FLAGS_REG))]
- "reload_completed && SSE_REG_P (operands[0])"
+ "reload_completed"
[(set (match_dup 0) (match_dup 3))]
{
machine_mode mode = GET_MODE (operands[0]);
@@ -9398,8 +9399,7 @@
{
rtx tmp;
operands[0] = gen_rtx_REG (SImode,
- true_regnum (operands[0])
- + (TARGET_64BIT ? 1 : 2));
+ REGNO (operands[0]) + (TARGET_64BIT ? 1 : 2));
if (GET_CODE (operands[1]) == ABS)
{
tmp = GEN_INT (0x7fff);
@@ -10091,7 +10091,7 @@
(clobber (reg:CC FLAGS_REG))]
"GET_MODE (operands[0]) == GET_MODE (operands[1])
&& reload_completed
- && true_regnum (operands[0]) != true_regnum (operands[1])"
+ && REGNO (operands[0]) != REGNO (operands[1])"
[(const_int 0)]
{
machine_mode mode = GET_MODE (operands[0]);
@@ -10120,7 +10120,7 @@
(match_operand:QI 2 "const_int_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed
- && true_regnum (operands[0]) != true_regnum (operands[1])"
+ && REGNO (operands[0]) != REGNO (operands[1])"
[(set (match_dup 0)
(zero_extend:DI (mult:SI (match_dup 1) (match_dup 2))))]
{
@@ -17839,7 +17839,7 @@
(match_operand:SI 3 "immediate_operand"))
(const_int 0)]))]
"ix86_match_ccmode (insn, CCNOmode)
- && (true_regnum (operands[2]) != AX_REG
+ && (REGNO (operands[2]) != AX_REG
|| satisfies_constraint_K (operands[3]))
&& peep2_reg_dead_p (1, operands[2])"
[(parallel
@@ -17860,7 +17860,7 @@
(const_int 0)]))]
"! TARGET_PARTIAL_REG_STALL
&& ix86_match_ccmode (insn, CCNOmode)
- && true_regnum (operands[2]) != AX_REG
+ && REGNO (operands[2]) != AX_REG
&& peep2_reg_dead_p (1, operands[2])"
[(parallel
[(set (match_dup 0)
@@ -17881,7 +17881,7 @@
(const_int 0)]))]
"! TARGET_PARTIAL_REG_STALL
&& ix86_match_ccmode (insn, CCNOmode)
- && true_regnum (operands[2]) != AX_REG
+ && REGNO (operands[2]) != AX_REG
&& peep2_reg_dead_p (1, operands[2])"
[(parallel [(set (match_dup 0)
(match_op_dup 1
More information about the Gcc-patches
mailing list