Enabling -frename-registers?

[Wilco Dijkstra]

Bernd Schmidt wrote:
> On 05/04/2016 03:25 PM, Ramana Radhakrishnan wrote:
>> On ARM / AArch32 I haven't seen any performance data yet - the one place we are concerned 
>> about the impact is on Thumb2 code size as regrename may end up inadvertently putting more 
>> things in high registers. 
>
> In theory at least arm_preferred_rename_class is designed to make the  opposite happen. Bernd  

I do not see that working unfortunately - Thumb-2 codesize increases by a few percent even with -Os.
This is primarily due to replacing a low register with IP, which often changes a 16-bit instruction like:

    movs    r2, #8

into a 32-bit one:

    mov     ip, #8

This will also affect other targets with multiple instruction sizes. So I think it should check the 
size of the new instruction patterns and only accept a rename if it is not larger (certainly with -Os).


Also when people claim they can't see any benefit, did they check the codesize difference on SPEC2006?
On AArch64 codesize reduced uniformly due to fewer moves (and in a few cases significantly so). I expect
that to be true for other RISC targets. Simply put, reduced codesize at no performance loss = gain.

Wilco