[PATCH], Pr 71667, Fix PowerPC ISA 3.0 DImode Altivec load/store

[Michael Meissner]

As we discussed in the patch review, there were some issues with using %Y for
the ISA 3.0 instructions LXSD and STXSD.

I have rewritten the patch so that we have a new memory constraint (%wY) that
explicitly targets those instructions.  I went back to the mov{DF,DD} patterns
and changed their use of %o to %wY.

I removed the test that was generated from the XalanNamespacesStack.cpp source
that showed up the problem.

I have bootstrapped this on a little endian power8 system and there were no
regressions in the test suite.  I also built Spec 2006 for power9 with this
compiler, and the xalancbmk benchmark now builds.  I will kick off a big endian
build on a power7 system.

Assuming there are no regressions in power7, are these patches ok to install in
the trunk, and backport to GCC 6.2 after a burn-in period?

2016-06-28  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71667
	* config/rs6000/constraints.md (wY constraint): New constraint to
	match the requirements for the LXSD and STXSD instructions.
	* config/rs6000/predicates.md (offsettable_mem_14bit_operand): New
	predicate to match the requirements for the LXSD and STXSD
	instructions.
	* config/rs6000/rs6000.md (mov<mode>_hardfloat32, FMOVE64 case):
	Use constaint wY for LXSD/STXSD instructions instead of 'o' or 'Y'
	to make sure that the bottom 2 bits of offset are 0, the address
	form is offsettable, and no updating is done in the address mode.
	(mov<mode>_hardfloat64, FMOVE64 case): Likewise.
	(movdi_internal32): Likewise
	(movdi_internal64): Likewise.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797