[PATCH, AARCH64] add qdf24xx tuning structure

James Greenhalgh james.greenhalgh@arm.com
Mon Jun 13 08:53:00 GMT 2016


On Fri, Jun 10, 2016 at 03:48:38PM -0700, Jim Wilson wrote:
> This adds a tuning structure for qdf24xx.  This was tested with an
> aarch64-linux bootstrap and a make check, with no regressions.  I also
> tested it with an x86_64-linux C make check to verify that I didn't
> break the testsuite for non aarch64 targets.
> 
> I had to change one testcase because it assumes that a divide by
> constant will always be emitted as a multiply.  That actually depends
> on the relative costs of multiply, shift, and divide instructions.  I
> ended up with a divide instruction for my target, as it has reasonably
> fast divide instructions.  I fixed it by adding a -mtune=cortex-a53
> option for aarch64 to ensure that we always get the multiply insn.
> 
> Index: config/arm/aarch-cost-tables.h
> ===================================================================
> --- config/arm/aarch-cost-tables.h	(revision 237273)
> +++ config/arm/aarch-cost-tables.h	(working copy)
> @@ -537,4 +537,107 @@ const struct cpu_cost_table xgene1_extra_costs =
>    }
>  };
>  
> +const struct cpu_cost_table qdf24xx_extra_costs =
> +{

<...snip...>

> +  {
> +    /* FP SFmode */
> +    {
> +      COSTS_N_INSNS (6),      /* div.  */
> +      COSTS_N_INSNS (5),       /* mult.  */
> +      COSTS_N_INSNS (5),       /* mult_addsub. */
> +      COSTS_N_INSNS (5),       /* fma.  */
> +      COSTS_N_INSNS (3),       /* addsub.  */
> +      COSTS_N_INSNS (1),       /* fpconst. */
> +      COSTS_N_INSNS (1),       /* neg.  */
> +      COSTS_N_INSNS (2),       /* compare.  */
> +      COSTS_N_INSNS (4),       /* widen.  */
> +      COSTS_N_INSNS (4),       /* narrow.  */
> +      COSTS_N_INSNS (4),       /* toint.  */
> +      COSTS_N_INSNS (4),       /* fromint.  */
> +      COSTS_N_INSNS (2)        /* roundint.  */
> +    },
> +    /* FP DFmode */
> +    {
> +      COSTS_N_INSNS (11),      /* div.  */
> +      COSTS_N_INSNS (6),       /* mult.  */
> +      COSTS_N_INSNS (6),       /* mult_addsub.  */
> +      COSTS_N_INSNS (6),       /* fma.  */
> +      COSTS_N_INSNS (3),       /* addsub.  */
> +      COSTS_N_INSNS (1),       /* fpconst.  */
> +      COSTS_N_INSNS (1),       /* neg.  */
> +      COSTS_N_INSNS (2),       /* compare.  */
> +      COSTS_N_INSNS (4),       /* widen.  */
> +      COSTS_N_INSNS (4),       /* narrow.  */
> +      COSTS_N_INSNS (4),       /* toint.  */
> +      COSTS_N_INSNS (4),       /* fromint.  */
> +      COSTS_N_INSNS (2)        /* roundint.  */
> +    }
> +  },

Have you seen my recent patch for Cortex-A57 that changes the costs there
to be relative to the cost of a floating-point register to floating-point
register move [1]? I found that gave me a number of
improvements due to comparisons in the compiler that assume a move in a
mode is cheap, and other costs will be defined relative to it.

Did you consider that for the qdf24xx costs?

Otherwise, the AArch64 parts look good to me, but you'll want to wait for
an ARM OK too.

Thanks,
James

[1]: https://gcc.gnu.org/ml/gcc-patches/2016-06/msg00251.html



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