[RFC][PATCH , ARM 2/8] Add RTL patterns for thumb1 push/pop

[Andre Vieira (lists)]

On 26/12/15 01:45, Thomas Preud'homme wrote:
> [Sending on behalf of Andre Vieira]
>
> Hello,
>
> This patch adds RTL patterns for the push and pop instructions for thumb1. These are needed by subsequent patches in the series.
>
> *** gcc/ChangeLog ***
> 2015-10-27  Andre Vieira        <andre.simoesdiasvieira@arm.com>
>              Thomas Preud'homme  <thomas.preudhomme@arm.com>
>
>          * gcc/config/arm/arm-ldmstm.nl (constr thumb): Enabled
>            stackpointer to be written/read.
>          * gcc/config/arm/ldmstm.md: Regenerated.
>          * gcc/config/arm/thumb1.md (*thumb1_pop_single): New.
>            (*thumb1_load_multiple_operation): New.
>          * gcc/config/arm/arm.c (thumb_pop): Fix of comment.
>
>
> diff --git a/gcc/config/arm/arm-ldmstm.ml b/gcc/config/arm/arm-ldmstm.ml
> index 62982df594d5d4a1407df359e927c66986a9788c..f3ee741e93927d8d44a9eccec8970b46a8984216 100644
> --- a/gcc/config/arm/arm-ldmstm.ml
> +++ b/gcc/config/arm/arm-ldmstm.ml
> @@ -63,7 +63,7 @@ let rec final_offset addrmode nregs =
>     | DB -> -4 * nregs
>
>   let constr thumb =
> -  if thumb then "l" else "rk"
> +  if thumb then "lk" else "rk"
>
>   let inout_constr op_type =
>     match op_type with
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index 06a6184ee0c4ed1a7cec1de4c1786e297cc57872..2223101fbf96bceb4beb3a7d6cb04162481dc3bf 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -23773,8 +23773,8 @@ thumb1_emit_multi_reg_push (unsigned long mask, unsigned long real_regs)
>     return insn;
>   }
>
> -/* Emit code to push or pop registers to or from the stack.  F is the
> -   assembly file.  MASK is the registers to pop.  */
> +/* Emit code to pop registers from the stack.  F is the assembly file.
> +   MASK is the registers to pop.  */
>   static void
>   thumb_pop (FILE *f, unsigned long mask)
>   {
> diff --git a/gcc/config/arm/ldmstm.md b/gcc/config/arm/ldmstm.md
> index ebb09ab86e799f3606e0988980edf3cd0189272b..8c0472e07799bd9d08759e35b6b98f3536d3d013 100644
> --- a/gcc/config/arm/ldmstm.md
> +++ b/gcc/config/arm/ldmstm.md
> @@ -43,7 +43,7 @@
>   (define_insn "*thumb_ldm4_ia"
>     [(match_parallel 0 "load_multiple_operation"
>       [(set (match_operand:SI 1 "low_register_operand" "")
> -          (mem:SI (match_operand:SI 5 "s_register_operand" "l")))
> +          (mem:SI (match_operand:SI 5 "s_register_operand" "lk")))
>        (set (match_operand:SI 2 "low_register_operand" "")
>             (mem:SI (plus:SI (match_dup 5)
>                     (const_int 4))))
> @@ -80,7 +80,7 @@
>
>   (define_insn "*thumb_ldm4_ia_update"
>     [(match_parallel 0 "load_multiple_operation"
> -    [(set (match_operand:SI 5 "s_register_operand" "+&l")
> +    [(set (match_operand:SI 5 "s_register_operand" "+&lk")
>             (plus:SI (match_dup 5) (const_int 16)))
>        (set (match_operand:SI 1 "low_register_operand" "")
>             (mem:SI (match_dup 5)))
> @@ -133,7 +133,7 @@
>
>   (define_insn "*thumb_stm4_ia_update"
>     [(match_parallel 0 "store_multiple_operation"
> -    [(set (match_operand:SI 5 "s_register_operand" "+&l")
> +    [(set (match_operand:SI 5 "s_register_operand" "+&lk")
>             (plus:SI (match_dup 5) (const_int 16)))
>        (set (mem:SI (match_dup 5))
>             (match_operand:SI 1 "low_register_operand" ""))
> @@ -491,7 +491,7 @@
>   (define_insn "*thumb_ldm3_ia"
>     [(match_parallel 0 "load_multiple_operation"
>       [(set (match_operand:SI 1 "low_register_operand" "")
> -          (mem:SI (match_operand:SI 4 "s_register_operand" "l")))
> +          (mem:SI (match_operand:SI 4 "s_register_operand" "lk")))
>        (set (match_operand:SI 2 "low_register_operand" "")
>             (mem:SI (plus:SI (match_dup 4)
>                     (const_int 4))))
> @@ -522,7 +522,7 @@
>
>   (define_insn "*thumb_ldm3_ia_update"
>     [(match_parallel 0 "load_multiple_operation"
> -    [(set (match_operand:SI 4 "s_register_operand" "+&l")
> +    [(set (match_operand:SI 4 "s_register_operand" "+&lk")
>             (plus:SI (match_dup 4) (const_int 12)))
>        (set (match_operand:SI 1 "low_register_operand" "")
>             (mem:SI (match_dup 4)))
> @@ -568,7 +568,7 @@
>
>   (define_insn "*thumb_stm3_ia_update"
>     [(match_parallel 0 "store_multiple_operation"
> -    [(set (match_operand:SI 4 "s_register_operand" "+&l")
> +    [(set (match_operand:SI 4 "s_register_operand" "+&lk")
>             (plus:SI (match_dup 4) (const_int 12)))
>        (set (mem:SI (match_dup 4))
>             (match_operand:SI 1 "low_register_operand" ""))
> @@ -877,7 +877,7 @@
>   (define_insn "*thumb_ldm2_ia"
>     [(match_parallel 0 "load_multiple_operation"
>       [(set (match_operand:SI 1 "low_register_operand" "")
> -          (mem:SI (match_operand:SI 3 "s_register_operand" "l")))
> +          (mem:SI (match_operand:SI 3 "s_register_operand" "lk")))
>        (set (match_operand:SI 2 "low_register_operand" "")
>             (mem:SI (plus:SI (match_dup 3)
>                     (const_int 4))))])]
> @@ -902,7 +902,7 @@
>
>   (define_insn "*thumb_ldm2_ia_update"
>     [(match_parallel 0 "load_multiple_operation"
> -    [(set (match_operand:SI 3 "s_register_operand" "+&l")
> +    [(set (match_operand:SI 3 "s_register_operand" "+&lk")
>             (plus:SI (match_dup 3) (const_int 8)))
>        (set (match_operand:SI 1 "low_register_operand" "")
>             (mem:SI (match_dup 3)))
> @@ -941,7 +941,7 @@
>
>   (define_insn "*thumb_stm2_ia_update"
>     [(match_parallel 0 "store_multiple_operation"
> -    [(set (match_operand:SI 3 "s_register_operand" "+&l")
> +    [(set (match_operand:SI 3 "s_register_operand" "+&lk")
>             (plus:SI (match_dup 3) (const_int 8)))
>        (set (mem:SI (match_dup 3))
>             (match_operand:SI 1 "low_register_operand" ""))
> diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
> index 7e3bcb465385031b7350397fb8fb0e0c0a467fb0..d2a0420a2e9c71bb954d134fb88a86d694cf786d 100644
> --- a/gcc/config/arm/thumb1.md
> +++ b/gcc/config/arm/thumb1.md
> @@ -1819,4 +1819,32 @@
>     }"
>     [(set_attr "type" "mov_reg")]
>   )
> +
> +(define_insn "*thumb1_load_multiple_with_writeback"
> +  [(match_parallel 0 "load_multiple_operation"
> +    [(set (match_operand:SI 1 "s_register_operand" "+kl")
> +	  (plus:SI (match_dup 1)
> +		   (match_operand:SI 2 "const_int_I_operand" "I")))
> +     (set (match_operand:SI 3 "s_register_operand" "=kl")
> +	  (mem:SI (match_dup 1)))])]
> +  "TARGET_THUMB1 && (reload_in_progress || reload_completed)"
> +  {
> +    arm_output_multireg_pop (operands, /*return_pc=*/ false,
> +				       /*cond=*/ const_true_rtx,
> +				       /*reverse=*/ false,
> +				       /*update=*/ true);
> +    return "";
> +  }
> +  [(set_attr "type" "load4")]
> +)
> +
> +;; Pop a single register as its size is preferred over a post-incremental load
> +(define_insn "*thumb1_pop_single"
> +  [(set (match_operand:SI 0 "low_register_operand" "=l")
> +	(mem:SI (post_inc:SI (reg:SI SP_REGNUM))))]
> +  "TARGET_THUMB1 && (reload_in_progress || reload_completed)"
> +  "pop\t{%0}"
> +  [(set_attr "type" "load1")
> +   (set_attr "length" "2")]
> +)
>
>
> We welcome any comment.
>
> Cheers,
>
> Andre
>
Hi,

Dropping this patch from the series as I realized it not required for 
subsequent patches.

Cheers,
Andre