[Patch AArch64] Restrict 16-bit sqrdml{sa}h instructions to FP_LO_REGS

James Greenhalgh james.greenhalgh@arm.com
Tue Jan 26 16:05:00 GMT 2016


Hi,

In their forms using 16-bit lanes, the sqrdmlah and sqrdmlsh instruction
available when compiling with -march=armv8.1-a are only usable with
a register number in the range 0 to 15 for operand 3, as gas will point
out:

  Error: register number out of range 0 to 15 at
    operand 3 -- `sqrdmlsh v2.4h,v4.4h,v23.h[5]'

This patch teaches GCC to avoid registers outside of this range when
appropriate, in the same fashion as we do for other instructions with
this limitation.

Tested on an internal testsuite targeting Neon intrinsics.

OK?

Thanks,
James

---
2016-01-25  James Greenhalgh  <james.greenhalgh@arm.com>

	* config/aarch64/aarch64.md
	(arch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Fix register
	constraints for	operand 3.
	(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Likewise.

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