[PATCH][AArch64] Handle CSEL of zero_extended operands in rtx costs

[Kyrill Tkachov]

Hi all,

This patch fixes the test gcc.target/aarch64/pr66776.c for -mcpu=cortex-a53.
Currently we don't handle the (if_then_else (cond) (zero_extend r1) (zero_extend r2))
form of CSEL, so we end up recursing into the operands of the if_then_else and for some CPUs
reject the combination. We end up generating two UXTW instructions followed by a CSEL rather
than a single CSEL on the w-regs. Such is the case for -mcpu=cortex-a53.

This small patch fixes that by catching the zero_extended operands and extracting their
inner regs properly for further costing in aarch64_if_then_else_costs.

With this patch the aforementioned test now passes with -mcpu=cortex-a53.
Bootstrapped and tested on aarch64-none-linux-gnu.

Ok for trunk?
Thanks,
Kyrill

2016-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/aarch64/aarch64.c (aarch64_if_then_else_costs): Handle
     CSEL of zero_extended registers.
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