[PATCH][AArch64] Replace insn to zero up DF register
Fri Feb 26 22:43:00 GMT 2016
On 02/26/16 06:37, Wilco Dijkstra wrote:
> Evandro Menezes <firstname.lastname@example.org> wrote:
>> I have a question though: is it necessary to add the "fp" and "simd"
>> attributes to both movsf_aarch64 and movdf_aarch64 as well?
> You need at least the "simd" attribute, but providing "fp" as well is clearer
> (in principle the TARGET_FLOAT check in the pattern condition is
> redundant as a result, but the movhf and movtf patterns already do both).
> Also you want to use the smallest possible SIMD size as these are
> scalar operations and some microarchitectures execute 64-bit operations
> more efficiently than 128-bit ones, so:
> mov\\t%0.h, %w1
> + movi\\t%0.4h, #0
> umov\\t%w0, %1.h
> fmov\\t%s0, %w1
> + movi\\t%0.2s, #0
> fmov\\t%w0, %s1
> With those changes it should be ready for commit once you get the OK from James/Marcus.
Replace insn to zero up SIMD registers
(*movhf_aarch64): Add "movi %0, #0" to zero up register.
(*movsf_aarch64): Likewise and add "simd" and "fp" attributes.
Please, verify the new "simd" and "fp" attributes for SF and DF.
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