[PATCH, rs6000] Add -maltivec=be semantics in LE mode for vec_ld and vec_st

[Ulrich Weigand]

Hi Bill,

> 2014-02-20  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
> 
> 	* config/rs6000/altivec.md (altivec_lvxl): Rename as
> 	*altivec_lvxl_<mode>_internal and use VM2 iterator instead of
> 	V4SI.
> 	(altivec_lvxl_<mode>): New define_expand incorporating
> 	-maltivec=be semantics where needed.

I just noticed that this:

> -(define_insn "altivec_lvxl"
> +(define_expand "altivec_lvxl_<mode>"
>    [(parallel
> -    [(set (match_operand:V4SI 0 "register_operand" "=v")
> -	  (match_operand:V4SI 1 "memory_operand" "Z"))
> +    [(set (match_operand:VM2 0 "register_operand" "=v")
> +	  (match_operand:VM2 1 "memory_operand" "Z"))
>       (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
>    "TARGET_ALTIVEC"
> -  "lvxl %0,%y1"
> +{
> +  if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
> +    {
> +      altivec_expand_lvx_be (operands[0], operands[1], <MODE>mode, UNSPEC_SET_VSCR);
> +      DONE;
> +    }
> +})
> +
> +(define_insn "*altivec_lvxl_<mode>_internal"
> +  [(parallel
> +    [(set (match_operand:VM2 0 "register_operand" "=v")
> +	  (match_operand:VM2 1 "memory_operand" "Z"))
> +     (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
> +  "TARGET_ALTIVEC"
> +  "lvx %0,%y1"
>    [(set_attr "type" "vecload")])

now causes vec_ldl to emit the lvx instead of the lvxl instruction.
I assume this was not actually intended?

Bye,
Ulrich

-- 
  Dr. Ulrich Weigand
  GNU/Linux compilers and toolchain
  Ulrich.Weigand@de.ibm.com