[PATCH][AArch64] Split X-reg UBFIZ into W-reg LSL when possible

[Kyrill Tkachov]

Hi all,

Similar to the previous patch this transforms X-reg UBFIZ instructions into W-reg LSL instructions
when the UBFIZ operands add up to 32, so we can take advantage of the implicit zero-extension to DImode
when writing to a W-register.

This is done by splitting the existing *andim_ashift<mode>_bfi pattern into its two SImode and DImode
specialisations and changing the DImode pattern into a define_insn_and_split that splits into a
zero-extended SImode ashift when the operands match up.

So for the code in the testcase we generate:
LSL     W0, W0, 5

instead of:
UBFIZ   X0, X0, 5, 27

Bootstrapped and tested on aarch64-none-linux-gnu.

Since we're in stage 3 perhaps this is not for GCC 6, but it is fairly low risk.
I'm happy for it to wait for the next release if necessary.

Thanks,
Kyrill

2016-12-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * config/aarch64/aarch64.md (*andim_ashift<mode>_bfiz): Split into...
     (*andim_ashiftsi_bfiz): ...This...
     (*andim_ashiftdi_bfiz): ...And this.  Add split to ashift when
     possible.

2016-12-08  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

     * gcc.target/aarch64/ubfiz_lsl_1.c: New test.
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