[ARM][PATCH] Add support for overflow add, sub, and neg operations

[Yvan Roux]

Hi Michael,

On 2 August 2016 at 11:25, Kyrill Tkachov <kyrylo.tkachov@foss.arm.com> wrote:
> Hi Michael,
>
>
> On 02/08/16 09:13, Michael Collison wrote:
>>
>> Hi,
>>
>> This patch improves code generations for builtin arithmetic overflow
>> operations for the arm backend. As an example for a simple test case such
>> as:
>>
>> int
>> fn3 (int x, int y, int *ovf)
>> {
>>    int res;
>>    *ovf = __builtin_sadd_overflow (x, y, &res);
>>    return res;
>> }
>>
>> Current trunk at -O2 generates
>>
>> fn3:
>>          @ args = 0, pretend = 0, frame = 0
>>          @ frame_needed = 0, uses_anonymous_args = 0
>>          @ link register save eliminated.
>>          cmp     r1, #0
>>          mov     r3, #0
>>          add     r1, r0, r1
>>          blt     .L4
>>          cmp     r1, r0
>>          blt     .L3
>> .L2:
>>          str     r3, [r2]
>>          mov     r0, r1
>>          bx      lr
>> .L4:
>>          cmp     r1, r0
>>          ble     .L2
>> .L3:
>>          mov     r3, #1
>>          b       .L2
>>
>> With the patch this now generates:
>>
>>         adds    r0, r0, r1
>>         movvs   r3, #1
>>         movvc   r3, #0
>>         str     r3, [r2]
>>         bx      lr
>>
>> Ok for trunk?
>
>
> Ok assuming bootstrap and test on arm-none-linux-gnueabihf is clean.
> with a couple of ChangeLog nits below.
> Thanks for working through the iterations.

There is also a small coding style issue in this comment (2 spaces are
needed after the .)

+/* Generate RTL for a conditional branch with rtx comparison CODE in
+   mode CC_MODE. The destination of the unlikely conditional branch
+   is LABEL_REF.  */

Cheers,
Yvan

> Thanks,
> Kyrill
>
>
>>
>> 2016-07-27  Michael Collison <michael.collison@linaro.org>
>>           Michael Collison <michael.collison@arm.com>
>
>
> Two spaces between name and email address.
>
>
>>       * config/arm/arm-modes.def: Add new condition code mode CC_V
>>       to represent the overflow bit.
>>       * config/arm/arm.c (maybe_get_arm_condition_code):
>>       Add support for CC_Vmode.
>>       (arm_gen_unlikely_cbranch): New function to generate common
>>       rtl conditional branches for overflow patterns.
>>       * config/arm/arm-protos.h: Add prototype for
>>       arm_gen_unlikely_cbranch.
>>       * config/arm/arm.md (addv<mode>4, add<mode>3_compareV,
>>       addsi3_compareV_upper): New patterns to support signed
>>       builtin overflow add operations.
>>       (uaddv<mode>4, add<mode>3_compareC, addsi3_compareV_upper):
>>       New patterns to support unsigned builtin add overflow operations.
>>       (subv<mode>4, sub<mode>3_compare1): New patterns to support signed
>>       builtin overflow subtract operations,
>>       (usubv<mode>4): New patterns to support unsigned builtin subtract
>>       overflow operations.
>>       (negvsi3, negvdi3, negdi2_compare, negsi2_carryin_compare): New
>> patterns
>>       to support builtin overflow negate operations.
>>       * gcc.target/arm/builtin_saddl.c: New testcase.
>>       * gcc.target/arm/builtin_saddll.c: New testcase.
>>       * gcc.target/arm/builtin_uaddl.c: New testcase.
>>       * gcc.target/arm/builtin_uaddll.c: New testcase.
>>       * gcc.target/arm/builtin_ssubl.c: New testcase.
>>       * gcc.target/arm/builtin_ssubll.c: New testcase.
>>       * gcc.target/arm/builtin_usubl.c: New testcase.
>>       * gcc.target/arm/builtin_usubll.c: New testcase.
>
>
> Please make sure the testsuite entries go into the ChangeLog file in
> gcc/testsuite/
>