[PATCH 1/6] [ARC] Don't use drsub* instructions when selecting fpuda.

Claudiu Zissulescu Claudiu.Zissulescu@synopsys.com
Mon Apr 18 14:35:00 GMT 2016


The double precision floating point assist instructions are not
implementing the reverse double subtract instruction (drsub) found in
the FPX extension, hence, this patch.

OK to apply?
Claudiu

gcc/
2016-04-18  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (cpu_facility): Add fpx variant.
	(subdf3): Prohibit use reverse sub when assist operations option
	is enabled.
	* config/arc/fpx.md (subdf3_insn, *dsubh_peep2_insn): Allow drsub
	instructions only when FPX is enabled.
        * testsuite/gcc.target/arc/trsub.c: New test.
---
 gcc/config/arc/arc.md                |  8 +++++++-
 gcc/config/arc/fpx.md                |  7 ++++---
 gcc/testsuite/gcc.target/arc/trsub.c | 10 ++++++++++
 3 files changed, 21 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arc/trsub.c

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 4193d26..9766547 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -265,7 +265,7 @@
 		     - get_attr_length (insn)")))
 
 ; for ARCv2 we need to disable/enable different instruction alternatives
-(define_attr "cpu_facility" "std,av1,av2"
+(define_attr "cpu_facility" "std,av1,av2,fpx"
   (const_string "std"))
 
 ; We should consider all the instructions enabled until otherwise
@@ -277,6 +277,10 @@
 	 (and (eq_attr "cpu_facility" "av2")
 	      (not (match_test "TARGET_V2")))
 	 (const_string "no")
+
+	 (and (eq_attr "cpu_facility" "fpx")
+	      (match_test "TARGET_FP_DP_AX"))
+	 (const_string "no")
 	 ]
 	(const_string "yes")))
 
@@ -5709,6 +5713,8 @@
   "
    if (TARGET_DPFP)
     {
+     if (TARGET_FP_DP_AX && (GET_CODE (operands[1]) == CONST_DOUBLE))
+       operands[1] = force_reg (DFmode, operands[1]);
      if ((GET_CODE (operands[1]) == CONST_DOUBLE)
           || GET_CODE (operands[2]) == CONST_DOUBLE)
       {
diff --git a/gcc/config/arc/fpx.md b/gcc/config/arc/fpx.md
index b790600..2e11157 100644
--- a/gcc/config/arc/fpx.md
+++ b/gcc/config/arc/fpx.md
@@ -304,7 +304,8 @@
      drsubh%F0%F2 0,%H1,%L1
      drsubh%F0%F2 0,%3,%L1"
   [(set_attr "type" "dpfp_addsub")
-  (set_attr "length" "4,8,4,8")])
+   (set_attr "length" "4,8,4,8")
+   (set_attr "cpu_facility" "*,*,fpx,fpx")])
 
 ;; ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; ;; Peephole for following conversion
@@ -613,5 +614,5 @@
   drsubh%F0%F2 %H6, %H1, %L1
   drsubh%F0%F2 %H6, %3, %L1"
  [(set_attr "type" "dpfp_addsub")
-  (set_attr "length" "4,8,4,8")]
-)
+  (set_attr "length" "4,8,4,8")
+  (set_attr "cpu_facility" "*,*,fpx,fpx")])
diff --git a/gcc/testsuite/gcc.target/arc/trsub.c b/gcc/testsuite/gcc.target/arc/trsub.c
new file mode 100644
index 0000000..031935f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/trsub.c
@@ -0,0 +1,10 @@
+/* Tests if we generate rsub instructions when compiling using
+   floating point assist instructions.  */
+/* { dg-do compile } */
+/* { dg-options "-mfpu=fpuda -mcpu=arcem" } */
+
+double foo (double a)
+{
+  return ((double) 0.12 - a);
+}
+/* { dg-final { scan-assembler-not "drsub.*" } } */
-- 
1.9.1



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