[PATCH][AArch64] Add separate insn sched class for vector LDP & STP

Evandro Menezes e.menezes@samsung.com
Tue Sep 29 20:55:00 GMT 2015


It's been committed as 228253.

Thank y'all for playing.

Cheers,

-- 
Evandro Menezes                              Austin, TX


> -----Original Message-----
> From: Kyrill Tkachov [mailto:kyrylo.tkachov@arm.com]
> Sent: Tuesday, September 29, 2015 4:01
> To: Marcus Shawcroft; Evandro Menezes; gcc-patches@gcc.gnu.org
> Cc: James Greenhalgh; Ramana Radhakrishnan
> Subject: Re: [PATCH][AArch64] Add separate insn sched class for vector LDP &
> STP
> 
> 
> On 29/09/15 09:03, Marcus Shawcroft wrote:
> > On 29/09/15 00:52, Evandro Menezes wrote:
> >> In some micro-architectures the insns to load or store pairs of
> >> vector registers are implemented rather differently from those
> >> affecting lanes in vector registers.  Then, it's important that such
> >> insns be described likewise differently in the scheduling model.
> >>
> >> This patch adds the insn types neon_ldp{,_q} and neon_stp{,_q} apart
> >> from the current neon_load2_2reg_q and neon_store2_2reg_q types,
> >> respectively.
> >>
> > Hi,
> >
> > The AArch64 part of this is OK. Please wait for Kyrill or Ramana to
> > comment on ARM side.  Cheers /Marcus
> >
> 
> This is ok arm-wise. I see the instructions being modelled with this type
> don't have a direct arm equivalent anyway.
> Marcus' comment on the ChangeLog still apply.
> 
> Thanks,
> Kyrill
> 
> >> Thank you,
> >>
> >> -- Evandro Menezes
> >>
> >>
> >> 0001-AArch64-Add-separate-insn-sched-class-for-vector-LDP.patch
> >>
> >>
> >>   From 340249dcd2af8dfce486cb4f62d4eaf285c6a799 Mon Sep 17 00:00:00
> >> 2001
> >> From: Evandro Menezes<e.menezes@samsung.com>
> >> Date: Mon, 28 Sep 2015 15:00:00 -0500
> >> Subject: [PATCH] [AArch64] Add separate insn sched class for vector
> >> LDP & STP
> >>
> >> 2015-09-28  Evandro Menezes<e.menezes@samsung.com>
> >>
> >> 	gcc/
> >> 	* config/arm/types.md (neon_ldp, neon_ldp_q, neon_stp, neon_stp_q):
> >> 	add new insn types for vector load and store pairs.
> > s/add/Add/ and likewise the rest of the changelog comments.
> >
> >> 	* config/arm/cortex-a53.md (cortex_a53_f_load_2reg): add insn
> >> 	types "neon_ldp{,_q}".
> >> 	* config/arm/cortex-a57.md (neon_load_c): add insn types
> >> 	"neon_ldp{,_q}".
> >> 	(neon_store_complex): add insn types "neon_stp{,_q}".
> >> 	* config/aarch64/aarch64-simd.md (aarch64_be_movoi): add insn types
> >> 	"neon_{ldp,stp}_q".



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