[committed, PATCH] Change IA MCU processor from iamcu to lakemount

H.J. Lu hongjiu.lu@intel.com
Fri Sep 25 07:59:00 GMT 2015


The first IA MCU processor will be Lakemount.  This patch changes IA MCU
processor name from iamcu to lakemount.

Tested on Linux/x86-64 with -m32.  Checked into trunk.

H.J.
--
gcc/

	* config.gcc (x86_archs): Replace iamcu with lakemount.
	(with_cpu): Likewise.
	(with_arch): Likewise.
	* doc/invoke.texi: Likewise.
	* config/i386/i386-c.c (ix86_target_macros_internal): Replace
	PROCESSOR_IAMCU with PROCESSOR_LAKEMOUNT.  Replace
	__tune_iamcu__ with __tune_lakemount__.
	* config/i386/i386.c (iamcu_cost): Renamed to ...
	(lakemount_cost): This.
	(m_IAMCU): Renamed to ...
	(m_LAKEMOUNT): This.
	(initial_ix86_arch_features): Replace m_IAMCU with m_LAKEMOUNT.
	(processor_target_table): Replace "iamcu" with "lakemount".
	(processor_alias_table): Likewise.
	(ix86_issue_rate): Replace PROCESSOR_IAMCU with
	PROCESSOR_LAKEMOUNT.
	(ix86_adjust_cost): Likewise.
	(ia32_multipass_dfa_lookahead): Likewise.
	* config/i386/i386.h (processor_type): Likewise.
	* config/i386/x86-tune.def: Replace m_IAMCU with m_LAKEMOUNT.

gcc/testsuite/

	* gcc.target/i386/pr66749.c (dg-options): Replace -mtune=iamcu
	with -mtune=lakemount.
	* gcc.target/i386/pr66821.c (dg-options): Likewise.
	* gcc.target/i386/pr67329.c (dg-options): Likewise.
---
 gcc/config.gcc                          |  6 +++---
 gcc/config/i386/i386-c.c                |  6 +++---
 gcc/config/i386/i386.c                  | 16 ++++++++--------
 gcc/config/i386/i386.h                  |  2 +-
 gcc/config/i386/x86-tune.def            | 26 +++++++++++++-------------
 gcc/doc/invoke.texi                     |  4 ++--
 gcc/testsuite/gcc.target/i386/pr66749.c |  2 +-
 gcc/testsuite/gcc.target/i386/pr66821.c |  2 +-
 gcc/testsuite/gcc.target/i386/pr67329.c |  2 +-
 9 files changed, 33 insertions(+), 33 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f060e2f..41814b8 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -587,7 +587,7 @@ tm_defines="$tm_defines LIBC_GLIBC=1 LIBC_UCLIBC=2 LIBC_BIONIC=3 LIBC_MUSL=4"
 x86_archs="athlon athlon-4 athlon-fx athlon-mp athlon-tbird \
 athlon-xp k6 k6-2 k6-3 geode c3 c3-2 winchip-c6 winchip2 i386 i486 \
 i586 i686 pentium pentium-m pentium-mmx pentium2 pentium3 pentium3m \
-pentium4 pentium4m pentiumpro prescott iamcu"
+pentium4 pentium4m pentiumpro prescott lakemount"
 
 # 64-bit x86 processors supported by --with-arch=.  Each processor
 # MUST be separated by exactly one space.
@@ -3287,7 +3287,7 @@ esac
 if test x$with_cpu = x ; then
   case ${target} in
     i[34567]86-*-elfiamcu)
-      with_cpu=iamcu
+      with_cpu=lakemount
       ;;
     i[34567]86-*-*|x86_64-*-*)
       with_cpu=$cpu
@@ -3385,7 +3385,7 @@ if test x$with_arch = x ; then
       # and TARGET_SUBTARGET64_ISA_DEFAULT in config/i386/darwin.h.
       ;;
     i[34567]86-*-elfiamcu)
-      with_arch=iamcu
+      with_arch=lakemount
       ;;
     i[34567]86-*-*)
       # --with-fpmath sets the default ISA to SSE2, which is the same
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 5e583ae..86f2426 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -63,7 +63,7 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
       def_or_undef (parse_in, "__i486");
       def_or_undef (parse_in, "__i486__");
       break;
-    case PROCESSOR_IAMCU:
+    case PROCESSOR_LAKEMOUNT:
       /* Intel MCU is based on Intel Pentium CPU.  */
     case PROCESSOR_PENTIUM:
       def_or_undef (parse_in, "__i586");
@@ -293,8 +293,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
     case PROCESSOR_SKYLAKE_AVX512:
       def_or_undef (parse_in, "__tune_skylake_avx512__");
       break;
-    case PROCESSOR_IAMCU:
-      def_or_undef (parse_in, "__tune_iamcu__");
+    case PROCESSOR_LAKEMOUNT:
+      def_or_undef (parse_in, "__tune_lakemount__");
       break;
     case PROCESSOR_INTEL:
     case PROCESSOR_GENERIC:
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 8a26f68..193cabf 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -417,7 +417,7 @@ struct processor_costs pentium_cost = {
 };
 
 static const
-struct processor_costs iamcu_cost = {
+struct processor_costs lakemount_cost = {
   COSTS_N_INSNS (1),			/* cost of an add instruction */
   COSTS_N_INSNS (1) + 1,		/* cost of a lea instruction */
   COSTS_N_INSNS (1),			/* variable shift costs */
@@ -2085,7 +2085,7 @@ const struct processor_costs *ix86_cost = &pentium_cost;
 #define m_386 (1<<PROCESSOR_I386)
 #define m_486 (1<<PROCESSOR_I486)
 #define m_PENT (1<<PROCESSOR_PENTIUM)
-#define m_IAMCU (1<<PROCESSOR_IAMCU)
+#define m_LAKEMOUNT (1<<PROCESSOR_LAKEMOUNT)
 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
 #define m_NOCONA (1<<PROCESSOR_NOCONA)
@@ -2146,7 +2146,7 @@ unsigned char ix86_arch_features[X86_ARCH_LAST];
    ix86_arch_features based on the processor mask.  */
 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
   /* X86_ARCH_CMOV: Conditional move was added for pentiumpro.  */
-  ~(m_386 | m_486 | m_PENT | m_IAMCU | m_K6),
+  ~(m_386 | m_486 | m_PENT | m_LAKEMOUNT | m_K6),
 
   /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486.  */
   ~m_386,
@@ -2557,7 +2557,7 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
   {"i386", &i386_cost, 4, 3, 4, 3, 4},
   {"i486", &i486_cost, 16, 15, 16, 15, 16},
   {"pentium", &pentium_cost, 16, 7, 16, 7, 16},
-  {"iamcu", &iamcu_cost, 16, 7, 16, 7, 16},
+  {"lakemount", &lakemount_cost, 16, 7, 16, 7, 16},
   {"pentiumpro", &pentiumpro_cost, 16, 15, 16, 10, 16},
   {"pentium4", &pentium4_cost, 0, 0, 0, 0, 0},
   {"nocona", &nocona_cost, 0, 0, 0, 0, 0},
@@ -3313,7 +3313,7 @@ ix86_option_override_internal (bool main_args_p,
       {"i486", PROCESSOR_I486, CPU_NONE, 0},
       {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
       {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
-      {"iamcu", PROCESSOR_IAMCU, CPU_PENTIUM, 0},
+      {"lakemount", PROCESSOR_LAKEMOUNT, CPU_PENTIUM, 0},
       {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
       {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
       {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
@@ -26196,7 +26196,7 @@ ix86_issue_rate (void)
   switch (ix86_tune)
     {
     case PROCESSOR_PENTIUM:
-    case PROCESSOR_IAMCU:
+    case PROCESSOR_LAKEMOUNT:
     case PROCESSOR_BONNELL:
     case PROCESSOR_SILVERMONT:
     case PROCESSOR_KNL:
@@ -26383,7 +26383,7 @@ ix86_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn, int cost)
   switch (ix86_tune)
     {
     case PROCESSOR_PENTIUM:
-    case PROCESSOR_IAMCU:
+    case PROCESSOR_LAKEMOUNT:
       /* Address Generation Interlock adds a cycle of latency.  */
       if (insn_type == TYPE_LEA)
 	{
@@ -26593,7 +26593,7 @@ ia32_multipass_dfa_lookahead (void)
   switch (ix86_tune)
     {
     case PROCESSOR_PENTIUM:
-    case PROCESSOR_IAMCU:
+    case PROCESSOR_LAKEMOUNT:
       return 2;
 
     case PROCESSOR_PENTIUMPRO:
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 46fbe42..adc1fed 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2280,7 +2280,7 @@ enum processor_type
   PROCESSOR_I386,			/* 80386 */
   PROCESSOR_I486,			/* 80486DX, 80486SX, 80486DX[24] */
   PROCESSOR_PENTIUM,
-  PROCESSOR_IAMCU,
+  PROCESSOR_LAKEMOUNT,
   PROCESSOR_PENTIUMPRO,
   PROCESSOR_PENTIUM4,
   PROCESSOR_NOCONA,
diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
index 42a560b..414c718 100644
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -40,7 +40,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 
 /* X86_TUNE_SCHEDULE: Enable scheduling.  */
 DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
-          m_PENT | m_IAMCU | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
+          m_PENT | m_LAKEMOUNT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
 	  | m_INTEL | m_KNL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC)
 
 /* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
@@ -172,21 +172,21 @@ DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
    over esp subtraction.  */
 DEF_TUNE (X86_TUNE_SINGLE_PUSH, "single_push", m_386 | m_486 | m_PENT
-	  | m_IAMCU | m_K6_GEODE)
+	  | m_LAKEMOUNT | m_K6_GEODE)
 
 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
    over esp subtraction.  */
-DEF_TUNE (X86_TUNE_DOUBLE_PUSH, "double_push", m_PENT | m_IAMCU
+DEF_TUNE (X86_TUNE_DOUBLE_PUSH, "double_push", m_PENT | m_LAKEMOUNT
 	  | m_K6_GEODE)
 
 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
    over esp addition.  */
 DEF_TUNE (X86_TUNE_SINGLE_POP, "single_pop", m_386 | m_486 | m_PENT
-	  | m_IAMCU | m_PPRO)
+	  | m_LAKEMOUNT | m_PPRO)
 
 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
    over esp addition.  */
-DEF_TUNE (X86_TUNE_DOUBLE_POP, "double_pop", m_PENT | m_IAMCU)
+DEF_TUNE (X86_TUNE_DOUBLE_POP, "double_pop", m_PENT | m_LAKEMOUNT)
 
 /*****************************************************************************/
 /* Branch predictor tuning  		                                     */
@@ -226,7 +226,7 @@ DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_GENERIC)
 
 /* X86_TUNE_READ_MODIFY: Enable use of read-modify instructions such
    as "add mem, reg".  */
-DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_IAMCU | m_PPRO))
+DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMOUNT | m_PPRO))
 
 /* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions.   */
 DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
@@ -286,7 +286,7 @@ DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
 
 /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions.  */
 DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
-	  ~(m_PENT | m_IAMCU | m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL
+	  ~(m_PENT | m_LAKEMOUNT | m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL
 	    | m_K6))
 
 /* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions.  */
@@ -307,7 +307,7 @@ DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP, "use_himode_fiop",
 /* X86_TUNE_USE_SIMODE_FIOP: Enables use of x87 instructions with 32bit
    integer operand.  */
 DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
-          ~(m_PENT | m_IAMCU | m_PPRO | m_CORE_ALL | m_BONNELL
+          ~(m_PENT | m_LAKEMOUNT | m_PPRO | m_CORE_ALL | m_BONNELL
 	    | m_SILVERMONT | m_KNL | m_INTEL | m_AMD_MULTIPLE | m_GENERIC))
 
 /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp.  */
@@ -448,7 +448,7 @@ DEF_TUNE (X86_TUNE_SHIFT1, "shift1", ~m_486)
 /* X86_TUNE_ZERO_EXTEND_WITH_AND: Use AND instruction instead
    of mozbl/movwl.  */
 DEF_TUNE (X86_TUNE_ZERO_EXTEND_WITH_AND, "zero_extend_with_and",
-	  m_486 | m_PENT | m_IAMCU)
+	  m_486 | m_PENT | m_LAKEMOUNT)
 
 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
    and SImode multiply, but 386 and 486 do HImode multiply faster.  */
@@ -459,20 +459,20 @@ DEF_TUNE (X86_TUNE_PROMOTE_HIMODE_IMUL, "promote_himode_imul",
    into 16bit/8bit when resulting sequence is shorter.  For example
    for "and $-65536, reg" to 16bit store of 0.  */
 DEF_TUNE (X86_TUNE_FAST_PREFIX, "fast_prefix",
-	  ~(m_386 | m_486 | m_PENT | m_IAMCU))
+	  ~(m_386 | m_486 | m_PENT | m_LAKEMOUNT))
 
 /* X86_TUNE_READ_MODIFY_WRITE: Enable use of read modify write instructions
    such as "add $1, mem".  */
 DEF_TUNE (X86_TUNE_READ_MODIFY_WRITE, "read_modify_write",
-	  ~(m_PENT | m_IAMCU))
+	  ~(m_PENT | m_LAKEMOUNT))
 
 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
    than a MOV.  */
-DEF_TUNE (X86_TUNE_MOVE_M1_VIA_OR, "move_m1_via_or", m_PENT | m_IAMCU)
+DEF_TUNE (X86_TUNE_MOVE_M1_VIA_OR, "move_m1_via_or", m_PENT | m_LAKEMOUNT)
 
 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
    but one byte longer.  */
-DEF_TUNE (X86_TUNE_NOT_UNPAIRABLE, "not_unpairable", m_PENT | m_IAMCU)
+DEF_TUNE (X86_TUNE_NOT_UNPAIRABLE, "not_unpairable", m_PENT | m_LAKEMOUNT)
 
 /* X86_TUNE_PARTIAL_REG_STALL: Pentium pro, unlike later chips, handled
    use of partial registers by renaming.  This improved performance of 16bit
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 09c58ee..844d254 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -22219,8 +22219,8 @@ Intel i486 CPU@.  (No scheduling is implemented for this chip.)
 @itemx pentium
 Intel Pentium CPU with no MMX support.
 
-@item iamcu
-Intel MCU, based on Intel Pentium CPU.
+@item lakemount
+Intel Lakemount MCU, based on Intel Pentium CPU.
 
 @item pentium-mmx
 Intel Pentium MMX CPU, based on Pentium core with MMX instruction set support.
diff --git a/gcc/testsuite/gcc.target/i386/pr66749.c b/gcc/testsuite/gcc.target/i386/pr66749.c
index affda08..27c02ad 100644
--- a/gcc/testsuite/gcc.target/i386/pr66749.c
+++ b/gcc/testsuite/gcc.target/i386/pr66749.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target ia32 } */
 /* { dg-require-effective-target nonpic } */
-/* { dg-options "-O2 -miamcu -mtune=iamcu" } */
+/* { dg-options "-O2 -miamcu -mtune=lakemount" } */
 
 char a[10], b[10];
 
diff --git a/gcc/testsuite/gcc.target/i386/pr66821.c b/gcc/testsuite/gcc.target/i386/pr66821.c
index d32f03d..9d08b1a 100644
--- a/gcc/testsuite/gcc.target/i386/pr66821.c
+++ b/gcc/testsuite/gcc.target/i386/pr66821.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target ia32 } } */
-/* { dg-options "-O2 -fdump-tree-optimized -mtune=iamcu" } */
+/* { dg-options "-O2 -fdump-tree-optimized -mtune=lakemount" } */
 
 void bar (void);
 
diff --git a/gcc/testsuite/gcc.target/i386/pr67329.c b/gcc/testsuite/gcc.target/i386/pr67329.c
index a29dd5b..fec94eb 100644
--- a/gcc/testsuite/gcc.target/i386/pr67329.c
+++ b/gcc/testsuite/gcc.target/i386/pr67329.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target ia32 } } */
-/* { dg-options "-O3 -fno-tree-fre -fno-tree-pre -fdump-tree-optimized -mtune=iamcu" } */
+/* { dg-options "-O3 -fno-tree-fre -fno-tree-pre -fdump-tree-optimized -mtune=lakemount" } */
 
 int
 foo ()
-- 
2.4.3



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