[PATCH][AArch64 array_mode 8/8] Add d-registers to TARGET_ARRAY_MODE_SUPPORTED_P

[James Greenhalgh]

On Tue, Sep 15, 2015 at 10:14:43AM +0100, Alan Lawrence wrote:
> This adds an AARCH64_VALID_SIMD_DREG_MODE exactly paralleling the existing
> ...QREG... macro.
> 
> The new test now compiles (at -O3) to:
> 
> test_1:
>         add     v1.2s, v1.2s, v5.2s
>         add     v2.2s, v2.2s, v6.2s
>         add     v3.2s, v3.2s, v7.2s
>         add     v0.2s, v0.2s, v4.2s
>         ret
> 
> Whereas prior to this patch we got:
> 
> test_1:
>         add     v0.2s, v0.2s, v4.2s
>         sub     sp, sp, #160
>         add     v1.2s, v1.2s, v5.2s
>         add     v2.2s, v2.2s, v6.2s
>         add     v3.2s, v3.2s, v7.2s
>         str     d0, [sp, 96]
>         str     d1, [sp, 104]
>         str     d2, [sp, 112]
>         str     d3, [sp, 120]
>         ldp     x2, x3, [sp, 96]
>         stp     x2, x3, [sp, 128]
>         ldp     x0, x1, [sp, 112]
>         stp     x0, x1, [sp, 144]
>         ldr     d1, [sp, 136]
>         ldr     d0, [sp, 128]
>         ldr     d2, [sp, 144]
>         ldr     d3, [sp, 152]
>         add     sp, sp, 160
>         ret
> 
> I've tried to look for (the absence of) this extra code in a number of ways,
> all 3 scan...not's were previously failing (i.e. regex's were matching) but
> now pass.

OK.

Thanks,
James

> bootstrapped and check-gcc on aarch64-none-linux-gnu.
> 
> gcc/ChangeLog:
> 
> 	* config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): New.
> 	(AARCH64_VALID_SIMD_QREG_MODE): Correct mode->MODE.
> 
> 	* config/aarch64/aarch64.c (aarch64_array_mode_supported_p): Add
> 	AARCH64_VALID_SIMD_DREG_MODE.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/aarch64/vect-int32x2x4_1.c: New.

Yuck, mixed '-' and '_'. vect_int32x2x4_1.c seems better to me, though it
is your call.