[RFC AArch64][PR 63304] Handle literal pools for functions > 1 MiB in size.

Ramana Radhakrishnan ramana.radhakrishnan@foss.arm.com
Fri Sep 11 08:49:00 GMT 2015


On Thu, Aug 27, 2015 at 03:07:30PM +0100, Marcus Shawcroft wrote:
> On 27 July 2015 at 15:33, Ramana Radhakrishnan
> <ramana.radhakrishnan@foss.arm.com> wrote:
> 
> > <DATE>  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
> >
> >         PR target/63304
> >         * config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Handle
> >         nopcrelative_literal_loads.
> >         (aarch64_classify_address): Likewise.
> >         (aarch64_constant_pool_reload_icode): Define.
> >         (aarch64_secondary_reload): Handle secondary reloads for
> >         literal pools.
> >         (aarch64_override_options): Handle nopcrelative_literal_loads.
> >         (aarch64_classify_symbol): Handle nopcrelative_literal_loads.
> >         * config/aarch64/aarch64.md (aarch64_reload_movcp<ALLTF:mode><P:mode>):
> >         Define.
> >         (aarch64_reload_movcp<VALL:mode><P:mode>): Likewise.
> >         * config/aarch64/aarch64.opt: New option mnopc-relative-literal-loads
> >         * config/aarch64/predicates.md (aarch64_constant_pool_symref): New
> >         predicate.
> >         * doc/invoke.texi (mnopc-relative-literal-loads): Document.
> 
> This looks OK to me. It needs rebasing, but OK if the rebase is
> trival.  Default on is fine.  Hold off on the back ports for a couple
> of weeks.
> Cheers
> /Marcus

I didn't want to commit this and run off on holiday.

The rebase required is pretty much for Kyrill's work with saving
and restoring state for the target attributes stuff. So that's simple enough
and been tested ok.

I had forgotten there was a pre-requisite that requires a rebase after Alan's
recent work for F16, I've posted that again here after rebase for
approval.

https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02074.html

movtf is unnecessary as a separate expander. Move this to be with
the standard scalar floating point expanders.
    
Achieved by adding a new iterator and then using the same.
    
Tested cross aarch64-none-elf and no regressions.
    
Ramana
    
    	* config/aarch64/aarch.md (mov<mode>:GPF_F16): Use GPF_TF_F16.
      	(movtf): Delete.
     	* config/aarch64/iterators.md (GPF_TF_F16): New.
    	(GPF_F16): Delete.

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 2522982..58bb04a 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1043,8 +1043,8 @@
 })
 
 (define_expand "mov<mode>"
-  [(set (match_operand:GPF_F16 0 "nonimmediate_operand" "")
-	(match_operand:GPF_F16 1 "general_operand" ""))]
+  [(set (match_operand:GPF_TF_F16 0 "nonimmediate_operand" "")
+	(match_operand:GPF_TF_F16 1 "general_operand" ""))]
   ""
   {
     if (!TARGET_FLOAT)
@@ -1118,24 +1118,6 @@
                      f_loadd,f_stored,load1,store1,mov_reg")]
 )
 
-(define_expand "movtf"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "")
-	(match_operand:TF 1 "general_operand" ""))]
-  ""
-  {
-    if (!TARGET_FLOAT)
-      {
-	aarch64_err_no_fpadvsimd (TFmode, "code");
-	FAIL;
-      }
-
-    if (GET_CODE (operands[0]) == MEM
-        && ! (GET_CODE (operands[1]) == CONST_DOUBLE
-	      && aarch64_float_const_zero_rtx_p (operands[1])))
-      operands[1] = force_reg (TFmode, operands[1]);
-  }
-)
-
 (define_insn "*movtf_aarch64"
   [(set (match_operand:TF 0
 	 "nonimmediate_operand" "=w,?&r,w ,?r,w,?w,w,m,?r ,Ump,Ump")
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 475aa6e..c1a0ce2 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -38,8 +38,8 @@
 ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
 (define_mode_iterator GPF [SF DF])
 
-;; Iterator for General Purpose Float registers, inc __fp16.
-(define_mode_iterator GPF_F16 [HF SF DF])
+;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
+(define_mode_iterator GPF_TF_F16 [HF SF DF TF])
 
 ;; Integer vector modes.
 (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])




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