[PATCH 11/15][AArch64] vreinterpret(q?), vget_(low|high), vld1(q?)_dup

James Greenhalgh james.greenhalgh@arm.com
Fri Sep 4 10:18:00 GMT 2015

On Mon, Aug 24, 2015 at 10:17:19AM +0100, Alan Lawrence wrote:
> James Greenhalgh wrote:
> > 
> > Did you check that these actually emit the expected instruction?
> > 
> > Applying your patch set I see some fairly unpleasant code generation,
> > but I might have made an error, or perhaps you have another patch in
> > waiting?
> > 
> > Thanks,
> > James
> > 
> Yes, you are right, some of the code generation here is a bit grotty. However
> I think we should go for correctness and tests first, performance second.
> (There will be some tweaks to the iterators in aarch64-simd.md.)

In that case, these should be implemented as inline assembly blocks. As it
stands, the code generation for these intrinsics will be very poor with this
patch applied.

I'm going to hold off OKing this until I see a follow-up to fix the code
generation, either replacing those particular intrinsics with inline asm,
or doing the more comprehensive fix in the back-end.


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