[PATCH 12/15][AArch64] Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix

James Greenhalgh james.greenhalgh@arm.com
Fri Sep 4 09:54:00 GMT 2015


On Tue, Aug 25, 2015 at 11:47:02AM +0100, Alan Lawrence wrote:
> James Greenhalgh wrote:
> >>
> >> -  VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
> >> +  VAR2 (UNOP, vec_unpacks_hi_, 10, v4sf, v8hf)
> >
> > Should this not use the appropriate "BUILTIN_..." iterator?
> 
> Indeed; BUILTIN_VQ_HSF it is.
> 
> >>    VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
> >>    VAR1 (BINOP, float_truncate_hi_, 0, v8hf)
> 
> I could also use BUILTIN_VQ_HSF here (these two were added in a previous
> patch, before the VQ_HSF iterator was introduced). However, that goes against
> the principle that we should use the same iterator as the pattern (the
> pattern uses the <Vdbl> attribute of the VDF iterator), so I'm not sure
> whether that would be preferable (i.e. as a separate patch)?
> 
> >> -  VAR1 (UNOP, float_extend_lo_, 0, v2df)
> >> +  VAR2 (UNOP, float_extend_lo_, 0, v2df, v4sf)
> >
> > Likewise.
> 
> Similarly, the required iterator does not exist, as float_extend_lo_ is named
> after the <Vwide> attribute of the VDF iterator. The nearest equivalents I can
> see use two VAR1's rather than a VAR2, so I've updated the patch to do that too.
> 
> OK with those two changes? (patch attached and bootstrapped+check-gcc on
> aarch64-none-linux-gnu)

OK.

Thanks,
James



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