[PATCH][AArch64][4/5] Improve immediate generation

Wilco Dijkstra wdijkstr@arm.com
Wed Sep 2 12:36:00 GMT 2015


The code that emits a movw with an add/sub is hardly ever used, and all cases in actual code are
already covered by mov+movk, so it is redundant (an example of such an immediate is
0x00ffff0000000abcul).

Passes GCC regression tests/bootstrap. Minor changes in generated code due to movk being used
instead of add/sub (codesize remains the same).

ChangeLog:
2015-09-02  Wilco Dijkstra  <wdijkstr@arm.com>

	* gcc/config/aarch64/aarch64.c (aarch64_internal_mov_immediate):
	Remove redundant immediate generation code.

---
 gcc/config/aarch64/aarch64.c | 60 --------------------------------------------
 1 file changed, 60 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 0bc6b19..bd6e522 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1371,8 +1371,6 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
   int i;
   bool first;
   unsigned HOST_WIDE_INT val, val2;
-  bool subtargets;
-  rtx subtarget;
   int one_match, zero_match, first_not_ffff_match;
   int num_insns = 0;
 
@@ -1402,7 +1400,6 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
   /* Remaining cases are all for DImode.  */
 
   val = INTVAL (imm);
-  subtargets = optimize && can_create_pseudo_p ();
 
   one_match = 0;
   zero_match = 0;
@@ -1440,63 +1437,6 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
   if (zero_match == 2)
     goto simple_sequence;
 
-  mask = 0x0ffff0000UL;
-  for (i = 16; i < 64; i += 16, mask <<= 16)
-    {
-      HOST_WIDE_INT comp = mask & ~(mask - 1);
-
-      if (aarch64_uimm12_shift (val - (val & mask)))
-	{
-	  if (generate)
-	    {
-	      subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
-	      emit_insn (gen_rtx_SET (subtarget, GEN_INT (val & mask)));
-	      emit_insn (gen_adddi3 (dest, subtarget,
-				     GEN_INT (val - (val & mask))));
-	    }
-	  num_insns += 2;
-	  return num_insns;
-	}
-      else if (aarch64_uimm12_shift (-(val - ((val + comp) & mask))))
-	{
-	  if (generate)
-	    {
-	      subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
-	      emit_insn (gen_rtx_SET (subtarget,
-				      GEN_INT ((val + comp) & mask)));
-	      emit_insn (gen_adddi3 (dest, subtarget,
-				     GEN_INT (val - ((val + comp) & mask))));
-	    }
-	  num_insns += 2;
-	  return num_insns;
-	}
-      else if (aarch64_uimm12_shift (val - ((val - comp) | ~mask)))
-	{
-	  if (generate)
-	    {
-	      subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
-	      emit_insn (gen_rtx_SET (subtarget,
-				      GEN_INT ((val - comp) | ~mask)));
-	      emit_insn (gen_adddi3 (dest, subtarget,
-				     GEN_INT (val - ((val - comp) | ~mask))));
-	    }
-	  num_insns += 2;
-	  return num_insns;
-	}
-      else if (aarch64_uimm12_shift (-(val - (val | ~mask))))
-	{
-	  if (generate)
-	    {
-	      subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
-	      emit_insn (gen_rtx_SET (subtarget, GEN_INT (val | ~mask)));
-	      emit_insn (gen_adddi3 (dest, subtarget,
-				     GEN_INT (val - (val | ~mask))));
-	    }
-	  num_insns += 2;
-	  return num_insns;
-	}
-    }
-
   if (zero_match != 2 && one_match != 2)
     {
       for (i = 0; i < 64; i += 16, mask <<= 16)
-- 
1.8.3





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