[PATCH][AArch64] Replace insn to zero up DF register
Andrew Pinski
pinskia@gmail.com
Tue Oct 20 14:46:00 GMT 2015
On Tue, Oct 20, 2015 at 7:59 AM, Andrew Pinski <pinskia@gmail.com> wrote:
> On Tue, Oct 20, 2015 at 7:51 AM, Andrew Pinski <pinskia@gmail.com> wrote:
>> On Tue, Oct 20, 2015 at 7:40 AM, Evandro Menezes <e.menezes@samsung.com> wrote:
>>> In the existing targets, it seems that it's always faster to zero up a DF
>>> register with "movi %d0, #0" instead of "fmov %d0, xzr".
>>
>> I think for ThunderX 1, this change will not make a difference. So I
>> am neutral on this change.
>
> Actually depending on fmov is decoded in our pipeline, this change
> might actually be worse. Currently fmov with an immediate is 1 cycle
> while movi is two cycles. Let me double check how internally on how
> it is decoded and if it is 1 cycle or two.
Ok, my objections are removed as I talked with the architectures here
at Cavium and using movi is better in this case.
Thanks,
Andrew
>
> Thanks,
> Andrew
>
>>
>> Thanks,
>> Andrew
>>
>>>
>>> This patch modifies the respective pattern.
>>>
>>> Please, commit if it's alright.
>>>
>>> Thank you,
>>>
>>> --
>>> Evandro Menezes
>>>
More information about the Gcc-patches
mailing list