[PATCH] g++.dg/init/vbase1.C and g++.dg/cpp/ucn-1.C

[Mike Stump]

On Nov 16, 2015, at 6:02 AM, Renlin Li <renlin.li@arm.com> wrote:
> On 14/11/15 00:33, David Edelsohn wrote:
>> No RISC architecture can store directly to MEM, so the expected RTL in
>> g++.dg/init/vbase1.C is wrong.  I am adding XFAIL for PowerPC.  This
>> probably should be disabled for ARM and other RISC architectures.
> 
> I observed the same problem in arm.
> 
> This passes for aarch64 and mips as they have zero register to do that. However, other RISC might not have that feature, for example arm and RS6000 in this  case.

I fixed this with the below patch.  Tested on x86_64 linux, x86_64 darwin and my port.  If you want to list aarch64/arn and mips, please do.


	* g++.dg/init/vbase1.C: Only run on x86_64-*-* as this testcase
	isn't portable.

Index: g++.dg/init/vbase1.C
===================================================================
--- g++.dg/init/vbase1.C	(revision 230675)
+++ g++.dg/init/vbase1.C	(working copy)
@@ -42,4 +42,4 @@ int main(int, char**)
 // Verify that the SubB() mem-initializer is storing 0 directly into
 // this->D.whatever rather than into a stack temp that is then copied into the
 // base field.
-// { dg-final { scan-rtl-dump "set \[^\n\]*\n\[^\n\]*this\[^\n\]*\n\[^\n\]*const_int 0" "expand" { xfail { powerpc*-*-* } } } }
+// { dg-final { scan-rtl-dump "set \[^\n\]*\n\[^\n\]*this\[^\n\]*\n\[^\n\]*const_int 0" "expand" { target { x86_64-*-* } } } }