[PATCH] g++.dg/init/vbase1.C and g++.dg/cpp/ucn-1.C

[David Edelsohn]

On Mon, Nov 16, 2015 at 4:15 AM, Eric Botcazou <ebotcazou@adacore.com> wrote:
>> No RISC architecture can store directly to MEM, so the expected RTL in
>> g++.dg/init/vbase1.C is wrong.  I am adding XFAIL for PowerPC.  This
>> probably should be disabled for ARM and other RISC architectures.
>
> Some of them can store 0 directly to MEM though, for example SPARC.

As Mike said, this testcase isn't portable and needs to be limited to
the targets that support the particular idiom used in this testcase.

Thanks, David