[PATCH][ARM]Fix addsi3_compare_op2 pattern.

[Renlin Li]

Hi all,

This is a simply patch to adjust the assembly output for 
addsi3_compare_op2 rtx pattern in ARM backend.

According to the constraints, it's the second alternative which allows 
the second operand to be a constant.
The original pattern will trigger an ICE when the third alternative is 
chosen, and trying to output a constant while the second operand is a 
register.

This is triggered by my experimental backend changes. branch 5, 4.9 all 
have this problem.

arm-none-linux-gnueabihf bootstrap Okay, arm-none-eabi regression test Okay.

Okay to commit into trunk and backport to branch 5 and 4.9?

Regards,
Renlin Li

gcc/ChangeLog:

2015-11-12  Renlin Li  <renlin.li@arm.com>

     * config/arm/arm.md (addsi3_compare_op2): Make the order of
         assembly pattern consistent with constraint order.
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