[PATCH, ARM] Fix arm_subsi3_insn alternatives

[Yvan Roux]

Hi,

after the issue with duplicated alternatives exhibited by PR64208, I
checked the arm.md file and found that *arm_subsi3_insn has a
duplication where alt 4 is (r,rI,r) and alt 6 is (r,r,r), this results
in emitting an rsb instruction instead of a sub one, but it has also
an impact on scheduling as the type attribute affected to alt 4 is
alu_imm when it could only involve registers.

This is fixed by this small patch. Cross builded and regtested for
arm/armeb targets.
Ok for trunk (maybe for stage 1 as no PR is attached to that) ?

Cheers,
Yvan

 2105-03-24  Yvan Roux  <yvan.roux@linaro.org>

    * config/arm/arm.md ("*arm_subsi3_insn"): Fixed redundant alternatives.
-------------- next part --------------
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 164ac13..b4e50c2 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1177,9 +1177,9 @@
 
 ; ??? Check Thumb-2 split length
 (define_insn_and_split "*arm_subsi3_insn"
-  [(set (match_operand:SI           0 "s_register_operand" "=l,l ,l ,l ,r ,r,r,rk,r")
-	(minus:SI (match_operand:SI 1 "reg_or_int_operand" "l ,0 ,l ,Pz,rI,r,r,k ,?n")
-		  (match_operand:SI 2 "reg_or_int_operand" "l ,Py,Pd,l ,r ,I,r,r ,r")))]
+  [(set (match_operand:SI           0 "s_register_operand" "=l,l ,l ,l ,r,r,r,rk,r")
+	(minus:SI (match_operand:SI 1 "reg_or_int_operand" "l ,0 ,l ,Pz,I,r,r,k ,?n")
+		  (match_operand:SI 2 "reg_or_int_operand" "l ,Py,Pd,l ,r,I,r,r ,r")))]
   "TARGET_32BIT"
   "@
    sub%?\\t%0, %1, %2