[PATCH 12/15][AArch64] Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix

[James Greenhalgh]

On Tue, Jul 28, 2015 at 12:26:35PM +0100, Alan Lawrence wrote:
> commit 214fcc00475a543a79ed444f9a64061215397cc8
> Author: Alan Lawrence <alan.lawrence@arm.com>
> Date:   Wed Jan 28 13:01:31 2015 +0000
> 
>     AArch64 6/N: vcvt{,_high}_f32_f16 (using vect_par_cnst_hi_half, fixing bigendian indices)
> 
> diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
> index 8bcab72..9869b73 100644
> --- a/gcc/config/aarch64/aarch64-simd-builtins.def
> +++ b/gcc/config/aarch64/aarch64-simd-builtins.def
> @@ -361,11 +361,11 @@
>    BUILTIN_VSDQ_I_DI (UNOP, abs, 0)
>    BUILTIN_VDQF (UNOP, abs, 2)
>  
> -  VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
> +  VAR2 (UNOP, vec_unpacks_hi_, 10, v4sf, v8hf)

Should this not use the appropriate "BUILTIN_..." iterator?

>    VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
>    VAR1 (BINOP, float_truncate_hi_, 0, v8hf)
>  
> -  VAR1 (UNOP, float_extend_lo_, 0, v2df)
> +  VAR2 (UNOP, float_extend_lo_, 0, v2df, v4sf)

Likewise.

This looks OK to me with that fixed.

Thanks,
James