[PATCH, MIPS] I6400 scheduling

[Robert Suchanek]

Hi,

> > diff --git a/gcc/config/mips/i6400.md b/gcc/config/mips/i6400.md new
> > file mode 100644 index 0000000..101a20c
> > --- /dev/null
> > +++ b/gcc/config/mips/i6400.md
> > @@ -0,0 +1,142 @@
> > +;; DFA-based pipeline description for I6400.
> > +;;
> > +;; Copyright (C) 2007-2015 Free Software Foundation, Inc.
> 
> This should just be 2015.

Fixed.
 
> > diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-
> > cpus.def index fb4bae0..90836a3 100644
> > --- a/gcc/config/mips/mips-cpus.def
> > +++ b/gcc/config/mips/mips-cpus.def
> > @@ -50,13 +50,13 @@ MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, 33,
> > PTF_AVOID_BRANCHLIKELY)
> >     as mips32r2.  */
> >  MIPS_CPU ("mips32r3", PROCESSOR_M4K, 34, PTF_AVOID_BRANCHLIKELY)
> > MIPS_CPU ("mips32r5", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY) -
> > MIPS_CPU ("mips32r6", PROCESSOR_W32, 37, PTF_AVOID_BRANCHLIKELY)
> > +MIPS_CPU ("mips32r6", PROCESSOR_I6400, 37, PTF_AVOID_BRANCHLIKELY)
> >  MIPS_CPU ("mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY)
> >  /* ??? For now just tune the generic MIPS64r2 and above for 5KC as
> > well.   */
> >  MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY)
> > MIPS_CPU ("mips64r3", PROCESSOR_5KC, 66, PTF_AVOID_BRANCHLIKELY)
> > MIPS_CPU ("mips64r5", PROCESSOR_5KC, 68, PTF_AVOID_BRANCHLIKELY) -
> > MIPS_CPU ("mips64r6", PROCESSOR_W64, 69, PTF_AVOID_BRANCHLIKELY)
> > +MIPS_CPU ("mips64r6", PROCESSOR_I6400, 69, PTF_AVOID_BRANCHLIKELY)
> >
> >  /* MIPS I processors.  */
> >  MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0) @@ -166,3 +166,6 @@ MIPS_CPU
> > ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)  MIPS_CPU
> > ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY)  MIPS_CPU
> > ("octeon3", PROCESSOR_OCTEON3, 65, PTF_AVOID_BRANCHLIKELY)  MIPS_CPU
> > ("xlp", PROCESSOR_XLP, 65, PTF_AVOID_BRANCHLIKELY)
> > +
> > +/* MIPS64 Release 6 processors.  */
> > +MIPS_CPU ("i6400", PROCESSOR_I6400, 69, PTF_AVOID_BRANCHLIKELY)
> 
> I don't think this really matters but the PTF_AVOID_BRANCHLIKELY should
> not be necessary for R6 cores as there are no branch likely instructions.
> Changing this may also require an update to the option handling code
> in mips.c I don't know if it will try to enable branch likely if you
> remove this.

PTF_AVOID_BRANCHLIKELY replaced with 0 in all 3 cases.
AFAICS, there is no need to update the option handling code. The branch
likely will not be enabled as it is additionally guarded by ISA_HAS_BRANCHLIKELY.

> 
> OK with those changes.

I'll commit the updated patch once the build completes.

> Does the I6400 support load/store bonding? I seem to think it does but
> could be wrong. If it does then dealing with it in a follow up patch is
> OK with me.

It does support the load/store bonding.  I'll test and send another patch
for this.

Regards,
Robert