[nios2] [2/7] Adjust for reduced offsets in R2 load/store IO insns

[Sandra Loosemore]

Nios II has a group of load/store IO instructions that bypass the
normal memory cache; they're intended to be used for accessing
memory-mapped IO peripherals.  In the R2 re-encoding of the Nios II
instruction set, the constant offset field for these instructions has
been reduced from 16 bits to 12, so GCC needs a new constraint for
memory addresses for these instructions.

A "gotcha" here is that the new encodings don't play nicely with
GP-relative addressing.  %gprel is a 16-bit relocation, and adding a
12-bit equivalent didn't seem very useful as it would restrict the
size of the small data area to only 4K.  Moreover, we'd expect IO
peripherals to be mapped somewhere other than the normal small data
section.  So, we just tell GCC not to emit GP-relative addresses
for anything that might be used in a R2 load/store IO instruction.

Committed as r225792.

-Sandra

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