[PATCH][rtlanal.c][BE][1/2] Fix vector load/stores to not use ld1/st1

[Richard Sandiford]

Eric Botcazou <ebotcazou@adacore.com> writes:
>> Seems like the thread might have died down, so just wanted to ping it.
>> As Marcus says, this is holding up other patches so it'd be good to get
>> something in soon.  Would it be OK to commit the original patch or should
>> we wait?
>
> Yes, go ahead, but add a FIXME or ??? comment.

Thanks, here's what I installed.

Richard


gcc/
2015-01-25  Alan Hayward  <alan.hayward@arm.com>

	* rtlanal.c (subreg_get_info): Exit early for simple and common
	cases.

Index: gcc/rtlanal.c
===================================================================
--- gcc/rtlanal.c	2015-01-21 17:06:33.594664514 +0000
+++ gcc/rtlanal.c	2015-01-21 17:10:22.863830284 +0000
@@ -3440,6 +3440,22 @@ subreg_get_info (unsigned int xregno, ma
 	  info->offset = offset / regsize_xmode;
 	  return;
 	}
+      /* Quick exit for the simple and common case of extracting whole
+	 subregisters from a multiregister value.  */
+      /* ??? It would be better to integrate this into the code below,
+	 if we can generalize the concept enough and figure out how
+	 odd-sized modes can coexist with the other weird cases we support.  */
+      if (!rknown
+	  && WORDS_BIG_ENDIAN == REG_WORDS_BIG_ENDIAN
+	  && regsize_xmode == regsize_ymode
+	  && (offset % regsize_ymode) == 0)
+	{
+	  info->representable_p = true;
+	  info->nregs = nregs_ymode;
+	  info->offset = offset / regsize_ymode;
+	  gcc_assert (info->offset + info->nregs <= nregs_xmode);
+	  return;
+	}
     }
 
   /* Lowpart subregs are otherwise valid.  */