[RFC, PR target/65105] Use vector instructions for scalar 64bit computations on 32bit target

[Jeff Law]

On 08/21/2015 07:44 AM, Ilya Enkovich wrote:
>> Our of curiosity, what does LLVM do here in terms of costing
>> models?
>
> Unfortunately I have no idea where and how LLVM does this
> optimization. Will try to find out. For now I just try to follow a
> common sense and don't hurt any benchmark performance.
Sounds wise.  No reason we can't look at the overall heuristics they're 
using for when this optimization ought to fire.

>>
>> From a correctness standpoint, one of the interesting tests would
>> be to turn off all tuning -- ie, always convert if it's supposed to
>> be possible.  Then throw as much code as possible at it and see if
>> anything breaks.  Also a good time to instrument so that you can
>> then build testcases from real-world code.
>
> I did such testing previously for SPEC.
Excellent to hear.

 >  Now I also tried it for
> bootstrap and found issue with EH edges.  Fixed it in a new version.


When you track down the bootstrap failure, you might consider adding a
test for whatever went wrong to the suite if it's feasible.


>
> Thanks a lot for your review! Here is an updated version. Bootstrap
> is OK. Regression testing shows a fail in gcc.dg/lower-subreg-1.c. It
> happens because ior:DI is a subject for a new optimization and is not
> lowered by subreg pass. I see test had multiple modifications to be
> disabled on different targets. Will it actually be tested anywhere if
> I disable it for i386? Probably remove the test?

I'd twiddle the test to turn off your new pass.  Which leads to the
comment that your pass needs to be selectable via a -m argument.

Jeff