[PATCH][AARCH64]Use shl for vec_shr_<mode> rtx pattern.

[Marcus Shawcroft]

On 28 April 2015 at 16:41, Renlin Li <renlin.li@arm.com> wrote:
> Hi all,
>
> unsigned shift left dosen't support immediate shift. Previouly, gcc will
> generate asm instruction like this: "ushl d1, d0, 32", which is not a legal
> insn and will be rejected by assembler. This patch change the use of ushl in
> vec_shr_<mode> into shl.
>
> A test case is added, and it passes on both aarch64-none-elf and
> aarch64_be-none-elf tool-chain.
>
> Okay to commit?
>
> Regards,
> Renlin Li
>
> gcc/ChangeLog:
>
> 2015-04-28  Renlin Li  <renlin.li@arm.com>
>
>     * config/aarch64/aarch64-simd.md (vec_shr_<mode>): Use shl.
>
> gcc/testsuite/ChangeLog:
>
> 2015-04-28  Renlin Li  <renlin.li@arm.com>
>                     Alan Lawrence  <alan.lawrence@arm.com>
>
>     * gcc.target/aarch64/vect-reduc-or_1.c: New.


I think there is another issue here, this change:

     if (BYTES_BIG_ENDIAN)
-      return "ushl %d0, %d1, %2";
+      return "shl %d0, %d1, %2";
     else
       return "ushr %d0, %d1, %2";

is in the context of:

(define_insn "vec_shr_<mode>"
  [(set (match_operand:VD 0 "register_operand" "=w")
        (lshiftrt:VD (match_operand:VD 1 "register_operand" "w")
                     (match_operand:SI 2 "immediate_operand" "i")))]

The RTL describes a right shift of the bits within each element in the
vector while the optab expects  a right shift of the elements within
the vector?

/Marcus